公开(公告)号：WO2004053926A3

公开(公告)日：2004-11-25

申请号：PCT/EP0350958

申请日：2003-12-08

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： MALHOTRA SANDRA ,  SIMON ANDREW

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76844 ,  H01L21/76805 ,  H01L21/76865

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a dielectric layer (18). The dielectric layer is patterned so as to expose the metal conductor. A liner layer (24) is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor (14). In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer (26) is deposited into the pattern and covers the redeposited liner layer.

Abstract translation: 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体（14）被介电层（18）覆盖。 图案化电介质层以暴露金属导体。 然后将衬垫层（24）沉积到图案中。 然后对衬垫层进行氩溅射蚀刻以去除衬里层并暴露金属导体（14）。 在氩溅射蚀刻的过程中，衬里层被再沉积到图案的侧壁上。 最后，附加层（26）沉积到图案中并覆盖再沉积的衬里层。

公开(公告)号：AU2003300263A1

公开(公告)日：2004-06-30

申请号：AU2003300263

申请日：2003-12-08

Applicant: IBM

Inventor： MALHOTRA SANDRA ,  SIMON ANDREW

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/4763 ,  H01L21/768

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor. In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer is deposited into the pattern and covers the redeposited liner layer.

公开(公告)号：AU2003300263A8

公开(公告)日：2004-06-30

申请号：AU2003300263

申请日：2003-12-08

Applicant: IBM

Inventor： MALHOTRA SANDRA ,  SIMON ANDREW

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/4763 ,  H01L21/768

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor. In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer is deposited into the pattern and covers the redeposited liner layer.