バイナリコードの実行を制御する装置及び方法

    公开(公告)号:JP2015179318A

    公开(公告)日:2015-10-08

    申请号:JP2014055409

    申请日:2014-03-18

    Applicant: IBM

    Abstract: 【課題】自己書き換えコード(SMC)による書き換えが発生したことによって変換バイナリコードの一部が使用できなくなった状態から復帰する処理のパフォーマンスを向上する。【解決手段】DBTのランタイム50では、SMC検出部51が、オリジナルバイナリコードのSMCによる書き換えの発生を検出し、トレース特定部54が、SMCによる書き換えの発生の検出に応じて、オリジナルバイナリコードを最適化して得られた最適化バイナリコードのSMCによる書き換えの影響を受けるトレースを特定し、トレース修正部55が、複数のスレッドのうちのこのトレースを実行したスレッドが例外を発生するようにこのトレースを修正し、スレッド実行制御部56が、例外が発生した際に、SMCにより書き換えられたオリジナルバイナリコードのトレースを、例外を発生したスレッドが実行するように制御する。【選択図】図6

    Compiling method, program, and information processing apparatus
    2.
    发明专利
    Compiling method, program, and information processing apparatus 有权
    编译方法,程序和信息处理装置

    公开(公告)号:JP2013156971A

    公开(公告)日:2013-08-15

    申请号:JP2012019524

    申请日:2012-02-01

    CPC classification number: G06F9/3005 G06F8/4434 G06F9/45516

    Abstract: PROBLEM TO BE SOLVED: To provide a compiling method, a program and an information processing apparatus that are capable of lowering a CPU load and decreasing memory consumption by reducing guard codes which need to be embedded in a compiled code, when an indirect branch instruction is included in a machine language code to be compiled.SOLUTION: The compiling method implemented by an information processing apparatus includes the steps of: generating intermediate code from a trace, which is an instruction sequence described in a machine language; computing an offset between an address value, which is a base point of an indirect branch instruction, and a start address of a memory page, which includes a virtual address referred to by the information processing apparatus immediately after processing a first instruction; determining whether processing jumps to another memory page, using as an offset a value obtained by adding a displacement made by an indirect branch instruction, which is a second instruction subsequent to the first instruction; and optimizing the intermediate code by using the result of the determining step.

    Abstract translation: 要解决的问题:提供一种编译方法,程序和信息处理装置,其能够通过减少需要嵌入在编译代码中的保护代码来降低CPU负载并降低存储器消耗,当间接分支指令为 包括在要编译的机器语言代码中。解决方案:由信息处理设备实现的编译方法包括以下步骤:从作为机器语言描述的指令序列的轨迹生成中间代码; 计算作为间接分支指令的基点的地址值与存储器页的开始地址之间的偏移,所述偏移包括在处理第一指令之后立即由信息处理装置引用的虚拟地址; 确定处理是否跳到另一个存储器页面,将作为第一指令之后的第二指令的由间接转移指令进行的位移添加得到的值作为偏移量使用; 以及通过使用确定步骤的结果来优化中间代码。

    Fault tolerant computer system, method and program
    3.
    发明专利
    Fault tolerant computer system, method and program 有权
    容错计算机系统,方法和程序

    公开(公告)号:JP2011044078A

    公开(公告)日:2011-03-03

    申请号:JP2009193089

    申请日:2009-08-24

    Abstract: PROBLEM TO BE SOLVED: To provide a system for recovering from transient fault. SOLUTION: A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread and the trailing thread preferably being assigned to two different cores. At this time, the leading thread and the trailing thread are simultaneously executed, performing a buffering operation on a thread local area without performing a write operation on a shared memory. When the execution results of the two threads match each other, the content buffered to the thread local area is committed and written to the shared memory. When the execution results of the two threads do not match each other, the leading thread and the trailing thread are rolled back to a preceding commit point and re-executed. Matching of the execution results of the two threads can be guaranteed, to prevent an error by transient fault. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题:提供一种从瞬态故障中恢复的系统。

    解决方案:并行执行前导线程和后退线程。 假设每个部分没有发生瞬态故障,则在该部分中推测性地执行一个系统,其中前导线和尾线最好分配给两个不同的核。 此时,同时执行前导线程和后退线程,对线程本地区域执行缓冲操作,而不对共享存储器执行写入操作。 当两个线程的执行结果相互匹配时,缓存到线程局部区域的内容被提交并写入共享存储器。 当两个线程的执行结果彼此不匹配时,前导线程和后退线程将回滚到先前的提交点并重新执行。 可以保证两个线程执行结果的匹配,以防止短暂故障发生错误。 版权所有(C)2011,JPO&INPIT

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