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公开(公告)号：GB1279374A
公开(公告)日：1972-06-28
申请号：GB2108771
申请日：1971-04-19
Applicant: IBM
Inventor： TANG DONALD TAO-NAN
Abstract: 1279374 Digital transmission systems; coding and decoding INTERNATIONAL BUSINESS MACHINES CORP 19 April 1971 [24 Feb 1970] 21087/71 Heading H4P In a system for increasing transmission speed, binary sequences are recoded into other sequences whereby similar digits e.g. two l's cannot occur adjacently, the other sequences being transmitted over a raised cosine type of channel. As each transition is clearly identifiable, it is stated that transmission may be at a greater rate e.g. double speed than systems where two or more 1's are adjacent, also due to one bit period being interposed between each transition, the system has time to settle down during this period. A further advantage stated is that synchronization may be effected by sampling wave damped-oscillations at half bit periods (see Fig. 3, not shown). In the embodiment described five bit sequences are recoded into 7+1 bit sequences, those sequences with adjacent 1's not being used and the + 1 digit being a buffing digit between the sequences. Such sequences may be transmitted by a NRZI code i.e. where a transition from + 1 to -1 or conversely is a "1" and no transition is a "0". Sequences of 7 +1 digits may be transmitted during the same time period as a normal four digit code and further economy may be effected by selecting an optimum coding scheme. The recoding may allow any integral number of 0's between 1 and K: k may be limited to a determined integer or may equal infinity. It is stated that the arrangement enables either a d-limited (k = infinity) or dk limited (k is finite) transmission without interference at a rate of four times the skew symmetry frequency (twice cut off frequency) of a similar system employing codes with adjacent 1's. Coding and decoding arrangements are described in connection with Figs. 11 and 12 (not shown). The coder illustrated in Fig. 11 may be adapted from the general purpose dk-limited coder disclosed in Specification 1,239,113.
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Patent Agency Ranking
公开(公告)号：GB1277159A
公开(公告)日：1972-06-07
申请号：GB5991470
申请日：1970-12-17
Applicant: IBM
Inventor： KOBAYASHI HISASHI , TANG DONALD TAO-NAN
Abstract: 1277159 Data storage INTERNATIONAL BUSINESS MACHINES CORP 17 Dec 1970 [30 Dec 1969] 59914/70 Addition to 1277158 Heading G4C Binary sequences are converted into interleaved NRZI form, recorded, read and then encoded by a correlative level coding process having delay by more than one digit in its encoding function. The input sequence (kth bit being ak) is converted to interleaved NRZI form in which the kth bit b k is given by this being equivalent to dividing by 1 - D 2 then reducing mod 2. The interleaved NRZI form is recorded on magnetic tape, disc or drum, each 1 reversing the magnetization. On read-out, a conventional (differentiating) read head followed by a corrective filter with a cosine frequency characteristic performs the correlative encoding to produce bits c k according to this being equivalent to multiplying by 1 - D 2 . The result is then divided by 1 - D 2 in a first decoder which feeds a second decoder which multiplies by 1 - D 2 and takes the result mod 2, thus reproducing the original input sequence. If any digit at the output of the first decoder is other than 0 or 1, an error signal is produced by a level detector to give a warning to the operator or cause re-reading of the recorded data.
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公开(公告)号：DE2257929A1
公开(公告)日：1973-07-12
申请号：DE2257929
申请日：1972-11-25
Applicant: IBM
Inventor： KOBAYASHI HISASHI , TANG DONALD TAO-NAN
IPC: H03H15/00 , H04L25/03 , H04L25/497 , H04L25/04
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公开(公告)号：DE2221276A1
公开(公告)日：1972-12-07
申请号：DE2221276
申请日：1972-04-29
Applicant: IBM
Inventor： SHA RICHARD TZING-YEN , TANG DONALD TAO-NAN
Abstract: A recursive automatic equalizer with extremely fast convergence is disclosed. The equalizer includes a plurality of equalizer stages connected in cascade which first reduces impulse response of the communication channel to substantially zero. The front portion or sidelobe is reduced to substantially zero distortion by adjusting the tap settings of successive equalizer stages after successive iterations (the first iteration adjusts the tap settings of the first equalizer stage, the second iteration adjusts the tap settings of the second equalizer stage, and so on) such that after n iterations a given initial distortion D is reduced to substantially zero. The tap setting algorithm involved and the method of operating the cascaded equalizer is disclosed. Finally, after n iterations, the output signal which can be described by the function 1-A(n) is modified by the reciprocal of the foregoing function and, is this manner, the rear or trailing portion of an input signal which is to be equalized has its rear sidelobe distortion reduced to substantially zero leaving only the desired main pulse. Apparatus for modifying the trailing or rear end of a pulse to be equalized is also disclosed.
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公开(公告)号：DE2511402A1
公开(公告)日：1975-10-02
申请号：DE2511402
申请日：1975-03-15
Applicant: IBM
Inventor： LIN YEONG SHOW , LIU CHAO-NING , TANG DONALD TAO-NAN
Abstract: The data stored in a coincident block access bubble domain memory with bit-organized chips is encrypted by skewing or permuting selected word bits by predetermined amounts. This is implemented by providing an additional current loop on some or all of the chips which overlies the major loop pattern and has nodes at the similar vector poles of the major loop. The proper energization of selected ones of these additional current loops, under the control of a security key, inhibits or suppresses the advance of the bubble domains in the corresponding major loops for a predetermined number of cycles of the in-plane propagating field, thus skewing the word bits in these chips with respect to the remaining word bits in the unsuppressed chips. Decryption is accomplished by further inhibiting the same major loops for the necessary number of cycles to restore word bit synchronization throughout the memory.
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公开(公告)号：GB1277158A
公开(公告)日：1972-06-07
申请号：GB5401570
申请日：1970-11-13
Applicant: IBM
Inventor： TANG DONALD TAO-NAN , KOBAYASHI HISASHI
IPC: H04L1/00 , H04L25/48 , H04L25/497
Abstract: 1277158 Data transmission INTERNATIONAL BUSINESS MACHINES CORP 13 Nov 1970 [30 Dec 1969] 54015/70 Heading H4P A data transmission system uses correlation encoding with resulting increase in the number of signal value levels. In Fig. 2, an input signal train A(D)= a 0 + a 1 + D + a 2 D 2 + ... (where D is a time delay operator) where each signal can have any of m levels, is preceded at 10 (to prevent propagation of a chain of errors from a single error in the received transmission) by dividing by G(D)= g 0 + g 1 D + g 2 D 5 + ... and taking the resulting levels mod m, to give a train B(D)=b 0 + b 1 D + b 2 D 2 + .... This is correlatively encoded, 12, by multiplying by G(D) to give C(D)=c 0 + c 1 D + c 2 D 2 + ... in which each level can have any of M (greater than m) levels. C(D) is transmitted over a channel 14 and the received signal C 1 (D) decoded, 18, by dividing by G(D) to give B 1 (D) which in the absence of error equals B(D) and so has only m levels. If there are more than m levels, a level detector 22 (two thresholders feeding an OR gate) produces an error signal to give a warning or cause retransmission and inhibition of a decoder 20 which otherwise multiplies B 1 (D) by G(D) and takes the resulting levels mod m to give A 1 (D), which is equal to A(D) in the absence of errors. A modified system combines 10 and 12 into a unitary encoder, combines 18, 20, 22 into a unitary decoder and precedes the latter with a level splitter which standardizes the received levels to their nominal values after detecting them with thresholders. Fig. 4 shows the unitary encoder, assuming G(D)=g 0 + g 1 D + g 2 D 2 + ... 5 + g N D N , and is self-explanatory, the notation being as before. The unitary decoder is like Fig. 4 except that the mod m detector 34 follows the adder 46, the result from multiplier 36 is not taken mod m, and the output from this multiplier is also fed to a level detector to produce the error signal. If G(D) is 1 - D 2 , then b k =a k + b k-2 , mod m, and c k = b k - b k-2 . A(D) may have m = 3 and result from a preliminary 2-to-3 level transformation (no details).
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