Vertically-stacked co-planar transmission line structure for ic design
    2.
    发明专利
    Vertically-stacked co-planar transmission line structure for ic design 有权
    用于IC设计的垂直平面传输线结构

    公开(公告)号:JP2005094770A

    公开(公告)日:2005-04-07

    申请号:JP2004266306

    申请日:2004-09-14

    Abstract: PROBLEM TO BE SOLVED: To provide a vertically-stacked co-planar transmission line structure for an IC (integrated circuit) which exhibits loss/reflection characteristics superior to a conventional on-chip transmission line design. SOLUTION: A simple embodiment of the vertically-stacked co-planar transmission line structure is provided with a pair of micro-strips each of which is composed of a first and a second vertically-stacked co-planar conductors. Each conductor is provided with a metal layer, a next metal layer down and an intermediate connecting via layer between the metal layer and the next metal layer down. Characteristic impedance in a far wider range can be designed by the design of the on-chip transmission line of this structure and the insertion loss and the return loss with respect to a low-impedance source and a load termination device is largely improved. The structure is designed to be used for a long on-chip interconnection part which is susceptible to it. Characteristics superior to a conventional single-metal layer structure can be obtained and the characteristic impedance of the transmission line can be designed with a particular specification by this structure. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题:提供一种具有优于常规片上传输线设计的损耗/反射特性的用于IC(集成电路)的垂直堆叠共面传输线结构。 解决方案:垂直堆叠的共面传输线结构的简单实施例设置有一对微带,每个微带由第一和第二垂直堆叠的共面导体组成。 每个导体设置有金属层,下一个金属层和金属层和下一个金属层之间的中间连接通孔层。 可以通过该结构的片上传输线的设计来设计更宽范围内的特性阻抗,并且相对于低阻抗源和负载终端装置的插入损耗和回波损耗大大提高。 该结构设计用于易受其影响的长片上互连部件。 可以获得优于常规单金属层结构的特征,并且可以通过该结构以特定的规格设计传输线的特性阻抗。 版权所有(C)2005,JPO&NCIPI

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