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公开(公告)号：US3699530A
公开(公告)日：1972-10-17
申请号：US3699530D
申请日：1970-12-30
Applicant: IBM
Inventor： CAPOWSKI ROBERT S , UNTERBERGER ROBERT M , HORSMAN LARRY R
CPC classification number: G06F13/18 , G06F13/122
Abstract: A storage control unit (SCU) for a data processing system which buffers data fetch and data store requests from input/output channels for access to low-speed high-capacity interleaved logical storage units. Multiple dedicated buffers are provided for each channel in the storage control unit (SCU) to insure that all channels have an individual receptacle to transfer data to which cannot be made unavailable due to transfers by other channels. Priority resolution of requests from channels controls the use of the in bus from the channel to the SCU independently of subsequent priority resolution for use of the main storage. Once a channel transfers its storage address and data into its assigned SCU buffer, that buffer, based on the storage address contained within it, enters storage priority for the particular logical storage unit desired. In this manner, the single queue of channel requests is rearranged into four independent request queues based on logical storage addresses.
Abstract translation: 一种用于数据处理系统的存储控制单元（SCU），用于缓冲来自输入/输出通道的数据提取和数据存储请求，用于访问低速大容量交错逻辑存储单元。 为存储控制单元（SCU）中的每个通道提供多个专用缓冲器，以确保所有通道具有单独的插座以传输由于其他通道的传输而不能使其不可用的数据。 来自频道的请求的优先级分辨率控制从通道到SCU的总线的使用，独立于随后使用主存储的优先级分辨率。 一旦通道将其存储地址和数据传输到其分配的SCU缓冲器中，则该缓冲器基于其中包含的存储地址，为所需的特定逻辑存储单元输入存储优先级。 以这种方式，基于逻辑存储地址将信道请求的单个队列重新排列成四个独立的请求队列。
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公开(公告)号：FR2412121B1
公开(公告)日：1986-03-14
申请号：FR7831286
申请日：1978-10-31
Applicant: IBM
Inventor： COPE BERNARD , LYNCH KENNETH R , O'DONNELL DANIEL H , RODELL JOHN T , TURECHEK WILLIAM W , UNTERBERGER ROBERT M
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公开(公告)号：FR2412121A1
公开(公告)日：1979-07-13
申请号：FR7831286
申请日：1978-10-31
Applicant: IBM
Inventor： COPE BERNARD , LYNCH KENNETH R , O'DONNELL DANIEL H , RODELL JOHN T , TURECHEK WILLIAM W , UNTERBERGER ROBERT M
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