Abstract:
PROBLEM TO BE SOLVED: To provide a vertically-stacked co-planar transmission line structure for an IC (integrated circuit) which exhibits loss/reflection characteristics superior to a conventional on-chip transmission line design. SOLUTION: A simple embodiment of the vertically-stacked co-planar transmission line structure is provided with a pair of micro-strips each of which is composed of a first and a second vertically-stacked co-planar conductors. Each conductor is provided with a metal layer, a next metal layer down and an intermediate connecting via layer between the metal layer and the next metal layer down. Characteristic impedance in a far wider range can be designed by the design of the on-chip transmission line of this structure and the insertion loss and the return loss with respect to a low-impedance source and a load termination device is largely improved. The structure is designed to be used for a long on-chip interconnection part which is susceptible to it. Characteristics superior to a conventional single-metal layer structure can be obtained and the characteristic impedance of the transmission line can be designed with a particular specification by this structure. COPYRIGHT: (C)2005,JPO&NCIPI