公开(公告)号：DE3475152D1

公开(公告)日：1988-12-15

申请号：DE3475152

申请日：1984-05-23

Applicant: IBM ,  IBM FRANCE

Inventor： PLATEL GUY ,  SECONDO PIERRE ,  WIEST SYLVAIN

IPC: H04L13/08 ,  H04L12/64 ,  H04M3/00 ,  H04Q11/04 ,  H04L11/20

Abstract: Packets input to a buffer register (10) increment the contents of two counters (12,20). At 40ms intervals a real-time clock resets one counter (12) to zero after transferring its contents to a logic circuit (14) which addresses a memory (16). One output from the memory defines the buffer content (L), monitored by the other counter (20), at which the oldest packets in the buffer are suppressed by a cancelling device (22). Another output from the memory stipulates the number (x) of old packets which are to be suppressed. The real-time clock may be replaced by a comparator comparing the buffer output packet count with a fixed quantity.