公开(公告)号：US20210125581A1

公开(公告)日：2021-04-29

申请号：US17062871

申请日：2020-10-05

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan K. Bhiravabhatla ,  Arthur D. Hunter, JR. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

IPC: G09G5/36 ,  G06F12/0875 ,  G06F9/46 ,  G09G5/00

Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

公开(公告)号：US10909037B2

公开(公告)日：2021-02-02

申请号：US15493404

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Altug Koker ,  James A. Valerio ,  Prasoonkumar Surti

IPC: G09G5/36 ,  G06F12/0844 ,  G06T1/60

Abstract: A mechanism is described for facilitating memory address compression at computing devices. A method of embodiments, as described herein, includes coalescing slot addresses across multiple messages received from an execution unit, where the slot addresses are coalesced in groups based on memory cacheline addresses such that each of a set of slot addresses in a group have a memory cacheline address in common between them. The method may further include outputting the memory cacheline addresses.

公开(公告)号：US20200327635A1

公开(公告)日：2020-10-15

申请号：US16714862

申请日：2019-12-16

Applicant: Intel Corporation

Inventor： Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  James A. Valerio ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/50

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a processing array including multiple compute blocks, each compute block including multiple processing clusters and a thread dispatch unit to dispatch threads of a workload to the multiple compute blocks based on a parallelism metric, wherein the thread dispatch unit, based on the parallelism metric, is to perform one of a first operation and a second operation, the first operation to distribute threads across the multiple compute blocks and the second operation is to concentrate threads within one of the multiple compute blocks.

公开(公告)号：US10453427B2

公开(公告)日：2019-10-22

申请号：US15477030

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan Bhairavabhatla ,  Arthur D. Hunter, Jr. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

IPC: G09G5/36 ,  G06F9/46 ,  G06F12/0875 ,  G09G5/00 ,  G06F12/084 ,  G06F12/0811

Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

公开(公告)号：US10373285B2

公开(公告)日：2019-08-06

申请号：US15482810

申请日：2017-04-09

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  James A. Valerio ,  David Puffer ,  Abhishek R. Appu ,  Stephen Junkins

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888

Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

公开(公告)号：US20180308197A1

公开(公告)日：2018-10-25

申请号：US15493420

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  James A. Valerio ,  Eric J. Hoekstra ,  Arthur D. Hunter, JR.

IPC: G06T1/20 ,  G06F9/22 ,  G06F9/44 ,  G06T15/04

CPC classification number: G06T1/20 ,  G06F9/223 ,  G06F9/4496 ,  G06T15/04

Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.

公开(公告)号：US20180293693A1

公开(公告)日：2018-10-11

申请号：US15482810

申请日：2017-04-09

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  James A. Valerio ,  David Puffer ,  Abhishek R. Appu ,  Stephen Junkins

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/621 ,  G06F2212/656 ,  G06F2212/657 ,  G06T1/60

Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

公开(公告)号：US20160364828A1

公开(公告)日：2016-12-15

申请号：US14738679

申请日：2015-06-12

Applicant: INTEL CORPORATION

Inventor： James A. Valerio ,  Abhishek Venkatesh ,  Satyajit Sarangi ,  Michael Apodaca ,  Thomas F. Raoux ,  Hashem Hashemi ,  Rama S.B. Harihara

IPC: G06T1/20

Abstract: A mechanism is described for facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance on computing devices. A method of embodiments, as described herein, includes detecting a command stream associated with an application, where the command stream includes dispatches. The method may further include evaluating processing parameters relating to each of the dispatches, where evaluating further includes associating a first plan with one or more of the dispatches to transform the command stream into a transformed command stream. The method may further include associating, based on the first plan, a second plan to the one or more of the dispatches, where the second plan represents the transformed command stream. The method may further include executing the second plan, where execution of the second plan includes processing the transformed command stream in lieu of the command stream.

Abstract translation: 描述了一种机制，用于促进图形处理命令的动态运行时转换，以改善计算设备上的图形性能。 如本文所述的实施例的方法包括检测与应用相关联的命令流，其中命令流包括分派。 该方法还可以包括评估与每个调度有关的处理参数，其中评估进一步包括将第一计划与一个或多个调度相关联，以将命令流变换成变换的命令流。 该方法可以进一步包括：基于第一计划，将第二计划与一个或多个调度相关联，其中第二计划表示变换的命令流。 该方法还可以包括执行第二计划，其中第二计划的执行包括处理变换的命令流来代替命令流。

公开(公告)号：US11263152B2

公开(公告)日：2022-03-01

申请号：US16881271

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  James A. Valerio ,  Altug Koker ,  Prasoonkumar Surti ,  Balaji Vembu ,  Wenyin Fu ,  Bhushan M. Borole ,  Kamal Sinha

IPC: G06F12/12 ,  G06F12/128 ,  G06F12/0811 ,  G06F13/40 ,  G06T1/60 ,  G06F12/0897 ,  G06F12/084

Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.

公开(公告)号：US11176083B2

公开(公告)日：2021-11-16

申请号：US16847781

申请日：2020-04-14

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  James A. Valerio ,  Altug Koker ,  Abhishek R. Appu ,  Vasanth Ranganathan

IPC: G06F15/80 ,  G06T1/20

Abstract: A shared local memory data crossbar may be implemented in multiple stages. With this approach, the number of multiplexer cells can be reduced by fifty percent (50%) or more in some embodiments.