公开(公告)号：US20240112731A1

公开(公告)日：2024-04-04

申请号：US17957957

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Saima Siddiqui ,  Sarah Atanasov ,  Bernal Granados Alpizar ,  Uygar Avci

IPC: G11C13/00 ,  G11C11/22 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C11/22 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Techniques and mechanisms for operating a ferroelectric (FE) circuit element as a cell of a crossbar memory array. In an embodiment, the crossbar memory array comprises a bit line, a word line, and a data storage cell which includes a circuit element that extends to each of the bit line and the word line. The data storage cell is a FE circuit element which comprises terminals, each at a different respective one of the bit line or the word line, and one or more material layers between said terminals. One such layer comprises a FE nitride or a FE oxide. The FE circuit element is operable to selectively enable, or disable, operation as a diode. In another embodiment, the memory array is coupled to circuitry which corresponds a given mode of operation of the FE circuit element to a particular data bit value.

公开(公告)号：US20240112730A1

公开(公告)日：2024-04-04

申请号：US17957945

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Nazila Haratipour ,  Saima Siddiqui ,  Uygar Avci ,  Chia-Ching Lin

IPC: G11C13/00 ,  G11C11/22 ,  H01L45/00

CPC classification number: G11C13/0026 ,  G11C11/22 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  G11C2213/79

Abstract: Techniques and mechanisms for storing data with a memory cell which comprises a ferroelectric (FE) resistive junction. In an embodiment, a memory cell comprises a transistor and a FE resistive junction structure which is coupled to the transistor. The FE resistive junction structure comprises electrode structures, and a layer of a material which is between said electrode structures, wherein the material is a FE oxide or a FE semiconductor. The FE resistive junction structure selectively provides any of various levels of resistance, each to represent a respective one or more bits. A current flow through the FE resistive junction structure is characterized by thermionic emission through a Schottky barrier at an interface with one of the electrode structures. In another embodiment, the FE resistive junction structure further comprises one or more dielectric layers each between the layer of material and a different respective one of the electrode structures.