公开(公告)号：US20230012155A1

公开(公告)日：2023-01-12

申请号：US17782562

申请日：2020-12-04

Applicant: Khalifa University of Science and Technology

Inventor： Baker MOHAMMAD ,  Dima KILANI ,  Hani SALEH

IPC: G05F1/59 ,  G05F1/46 ,  G05F1/575 ,  H03K19/094

Abstract: Digital logic voltage regulators and related methods generate a regulated voltage via controlled switching of a power transistor. A digital logic voltage regulator includes a voltage level comparator, a power transistor, and a charge accumulator. The voltage level comparator generates a digital control signal that alternates between a first voltage level and a second voltage level in response to changes in relative voltage level between the regulated output voltage and the target voltage. The digital control signal causes the power transistor to switch from off to on in response to a reduction of the regulated output voltage relative to the target voltage and causes the power transistor to switch from on to off in response to an increase of the regulated output voltage relative to the target voltage. The charge accumulator decreases variation in the regulated output voltage that would occur without the charge accumulator.

公开(公告)号：US20230385115A1

公开(公告)日：2023-11-30

申请号：US18193635

申请日：2023-03-31

Applicant: Khalifa University of Science and Technology

Inventor： Athanasios STOURAITIS ,  Sakellariou VASILEIOS ,  Vasileios PALIOURAS ,  Ioannis KOURETAS ,  Hani SALEH

IPC: G06F9/50 ,  G06F7/72

CPC classification number: G06F9/5027 ,  G06F7/72

Abstract: A device can be used to implement a neural network in hardware. The device can include a processor, a memory, and a neural network accelerator. The neural network accelerator can be configured to implement, in hardware, a neural network by using a residue number system (RNS). At least one function of the neural network can have a corresponding approximation in the RNS system, and the at least one function can be provided by implementing the corresponding approximation in hardware.

公开(公告)号：US20230368017A1

公开(公告)日：2023-11-16

申请号：US18042994

申请日：2021-10-05

Applicant: Khalifa University of Science and Technology

Inventor： Mohammed F. TOLBA ,  Hani SALEH ,  Mahmoud AL-QUTAYRI ,  Baker MOHAMMAD

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: A method can be used to reduce the memory storage and energy used by deep neural networks. The method can include determining the weights associated with the deep neural network. An input feature map can be received and used with the weights to generate approximated weights. Using the approximated weights and the input feature map a convolution inference can be performed.