公开(公告)号：JPH11317775A

公开(公告)日：1999-11-16

申请号：JP1568599

申请日：1999-01-25

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KEITH EUGENE HOLENBACK ,  LATURELL DONALD R ,  WITMER STEVEN BROOKE

IPC: H04L25/49 ,  H04B14/06

Abstract: PROBLEM TO BE SOLVED: To decrease the number of communication lines needed for a serial interface between circuits while minimizing the jitters of a data clock recovered at a reception terminal. SOLUTION: A receiver system has a receiver 310 which receives a combined clock/data signal generated by combining a clock and data through 1-bit sigma data encoding and an edge detector 312 which detects an edge of the combined clock/data signal. A phase-locked loop 314 makes a lock according to the signal from the edge detector 312. A gate 318 derives the clock signal from the combined clock/data signal and a divider 320 divides the derived clock signal to generate a recovered clock signal 330 which corresponding to the bit rate of the original signal. A latch 322 driven by the phase-locked loop 314 derives the data signal from the combined clock/data signal.