公开(公告)号：EP0851470A1

公开(公告)日：1998-07-01

申请号：EP96830645.6

申请日：1996-12-24

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Sonego, Patrizia ,  Colabella, Elio ,  Bacchetta, Maurizio ,  Pividori, Luca

IPC: H01L21/3105 ,  H01L21/768 ,  H01L21/316

CPC classification number: H01L21/76819 ,  H01L21/31056 ,  H01L21/316

Abstract: A plurality of bit lines (6) are isolated from one another by a layered dielectric structure to provide a planar architecture onto which an optional conductive layer may be deposited.
The dielectric structure deposited with the method proposed in the instant Patent Application uses a highly planarizing dielectric layer (18) of the SOG type spun over a first insulating dielectric layer (17) and then solidified by means of a thermal polymerization process. The dielectric layers (17,18) are subjected to a etch-back treatment and to a subsequent thermal annealing treatment.

Abstract translation: 的位线的多个（6）彼此隔离由多层介电结构提供一种平面结构走上选择性设置的导电层的哪个可被沉积。 在本专利申请中提出的方法沉积在介电结构采用旋涂在第一电介质绝缘层（17），然后通过热聚合工艺来固化SOG的类型的高平坦化介电层（18）。 介电层（17,18）经受一个回蚀刻处理和随后的热退火处理。

公开(公告)号：EP0851479A1

公开(公告)日：1998-07-01

申请号：EP96830644.9

申请日：1996-12-24

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Sonego, Patrizia ,  Colabella, Elio ,  Bacchetta, Maurizio ,  Pividori, Luca

IPC: H01L21/768 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316

CPC classification number: H01L21/31051 ,  H01L21/31053 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837

Abstract: A method of depositing a dielectric ply structure to optimize the planarity of electronic devices which include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, such as the bit lines of memory cells.
The proposed solution in accordance with the principles of this invention allows the plurality of bit lines to be isolated from one another by a suitable dielectric ply structure to provide a planar architecture onto which an optional conductive layer may be deposited.
A plurality of word lines can be formed from the conductive layer by conventional photolithographic and dry-wet etching processes.
These lines intersect the plurality of bit lines to define a plurality of EPROM cells organized into a matrix-like topography.
The resulting planarization is adequate to avoid the typical shortcomings of the prior art, such as the lack of electrical continuity in the word lines or their excessively high electrical resistance from slenderized portions in the conductive sections due to poor planarity of the surfaces whereon the conductive layer is deposited.

Abstract translation: 沉积电介质层结构的方法，以优化该系统包括具有横跨基材铺设为离散线并联栅极区域有源元件的多个电子装置的平面：存储器单元的位线，如。 在雅舞蹈提出的解决方案与本发明的原理允许位线多元性到彼此通过一个合适的电介质帘布层结构来分离，以提供一个平面架构走上选择性设置的导电层的哪个可被沉积。 的字线的多个可以通过常规的光刻和干 - 湿蚀刻工艺，导电层来形成。 这些线相交的位线的多元化，以限定组织成矩阵状地形EPROM单元的复数。 将所得的平坦化是足够的，以避免现有技术,:的典型的短缺憾，例如在字线的缺乏电连续性或从导电部分由于表面的平坦性差，其上在导电层拉伸细化部分及其过高电阻 沉积。

公开(公告)号：EP0851463A1

公开(公告)日：1998-07-01

申请号：EP96830646.4

申请日：1996-12-24

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Sonego, Patrizia ,  Bacchetta, Maurizio

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/316

CPC classification number: H01L21/316 ,  H01L21/76819

Abstract: An intermediate dielectric layer on a semiconductor which incorporate non-volatile memories comprises an insulating dielectric layer (6) deposited from a liquid state source, e.g. by spinning, SOG type.
Solidified through a low-temperature thermal cycle and annealed by a rapid annealing step carried out in an oven under a gas stream, or by a slower annealing process. This insulating layer is encapsulated between two dielectric layers of silicon oxide (3,7) as deposited from a plasma.
Said rapid annealing step is also utilized to densify the upper dielectric layer (7) encapsulating the highly planarizing intermediate dielectric layer (6).

Abstract translation: 在其上包括的非易失性存储器的半导体的中间介电层包含对绝缘从液态源沉积的介电层（6），例如 通过纺丝，SOG类型。 通过低温热循环固化，通过快速退火步骤中退火的气流下在炉中进行，或通过较慢的退火工艺。 该绝缘层是从等离子体沉积的氧化硅（3.7）的两个介电层之间包封。 因此，所述快速退火步骤用于致密封装的高平坦化中间电介质层的上电介质层（7）（6）。