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    2.
    发明专利
    未知

    公开(公告)号：DE3585519D1

    公开(公告)日：1992-04-09

    申请号：DE3585519

    申请日：1985-12-23

    Applicant: SONY CORP

    Inventor： KITAMURA YOSHIO ,  TAKIZUKA HIROSHI ,  ISHIHARA TADAO

    IPC: G06F15/16 ,  G06F9/38 ,  G06F13/16 ,  G06F13/18 ,  G06F15/167 ,  G06F15/177 ,  G06T1/20 ,  G06T11/60 ,  G06F15/66

    Abstract: A system and method for processing an extraordinarily large amount of data is configured using ordinary versatile computers of relatively slow data processing speed. Tasking is shared to plural computers or processors connected to a system bus; a shared storage device provided in common for these processors is made up of plural memory banks connected to the system bus; data transferred between the processors and the memory banks are divided into a predetermined amounts of divisional data; the data are processed for each divisional data simultaneously in parallel fashion; and each memory bank is occupied simultaneously in parallel fashion in response to each memory request from each processor. An arbitrator is provided for acting on a single memory request in accordance with a predetermined priority order in the case where plural memory requests are outputted simultaneously to the same memory bank.

    5.
    发明专利
    未知

    公开(公告)号：AT73242T

    公开(公告)日：1992-03-15

    申请号：AT85309415

    申请日：1985-12-23

    Applicant: SONY CORP

    Inventor： KITAMURA YOSHIO ,  TAKIZUKA HIROSHI ,  ISHIHARA TADAO

    IPC: G06F15/16 ,  G06F9/38 ,  G06F13/16 ,  G06F13/18 ,  G06F15/167 ,  G06F15/177 ,  G06T1/20 ,  G06T11/60 ,  G06F15/66

    Abstract: A system and method for processing an extraordinarily large amount of data is configured using ordinary versatile computers of relatively slow data processing speed. Tasking is shared to plural computers or processors connected to a system bus; a shared storage device provided in common for these processors is made up of plural memory banks connected to the system bus; data transferred between the processors and the memory banks are divided into a predetermined amounts of divisional data; the data are processed for each divisional data simultaneously in parallel fashion; and each memory bank is occupied simultaneously in parallel fashion in response to each memory request from each processor. An arbitrator is provided for acting on a single memory request in accordance with a predetermined priority order in the case where plural memory requests are outputted simultaneously to the same memory bank.

    DATA PROCESSOR
    6.
    发明专利
    DATA PROCESSOR 未知

    公开(公告)号：AU578772B2

    公开(公告)日：1988-11-03

    申请号：AU5111885

    申请日：1985-12-11

    Applicant: SONY CORP

    Inventor： KITAMURA YOSHIO ,  TAKIZUKA HIROSHI ,  ISHIHARA TADAO

    IPC: G06F15/16 ,  G06F9/38 ,  G06F13/16 ,  G06F13/18 ,  G06F15/167 ,  G06F15/177 ,  G06T1/20 ,  G06T11/60 ,  G06F15/66

    Abstract: A system and method for processing an extraordinarily large amount of data is configured using ordinary versatile computers of relatively slow data processing speed. Tasking is shared to plural computers or processors connected to a system bus; a shared storage device provided in common for these processors is made up of plural memory banks connected to the system bus; data transferred between the processors and the memory banks are divided into a predetermined amounts of divisional data; the data are processed for each divisional data simultaneously in parallel fashion; and each memory bank is occupied simultaneously in parallel fashion in response to each memory request from each processor. An arbitrator is provided for acting on a single memory request in accordance with a predetermined priority order in the case where plural memory requests are outputted simultaneously to the same memory bank.

    DATA PROCESSOR
    7.
    发明专利
    DATA PROCESSOR 未知

    公开(公告)号：AU5111885A

    公开(公告)日：1986-07-03

    申请号：AU5111885

    申请日：1985-12-11

    Applicant: SONY CORP

    Inventor： KITAMURA YOSHIO ,  TAKIZUKA HIROSHI ,  ISHIHARA TADAO

    IPC: G06F15/16 ,  G06F9/38 ,  G06F13/16 ,  G06F13/18 ,  G06F15/167 ,  G06F15/177 ,  G06T1/20 ,  G06T11/60 ,  G06F15/66

    Abstract: A system and method for processing an extraordinarily large amount of data is configured using ordinary versatile computers of relatively slow data processing speed. Tasking is shared to plural computers or processors connected to a system bus; a shared storage device provided in common for these processors is made up of plural memory banks connected to the system bus; data transferred between the processors and the memory banks are divided into a predetermined amounts of divisional data; the data are processed for each divisional data simultaneously in parallel fashion; and each memory bank is occupied simultaneously in parallel fashion in response to each memory request from each processor. An arbitrator is provided for acting on a single memory request in accordance with a predetermined priority order in the case where plural memory requests are outputted simultaneously to the same memory bank.

    INFORMATION PROCESSING APPARATUS
    8.
    发明专利
    INFORMATION PROCESSING APPARATUS 未知

    公开(公告)号：CA1183977A

    公开(公告)日：1985-03-12

    申请号：CA378682

    申请日：1981-05-29

    Applicant: SONY CORP

    Inventor： TOMITA SHINJI ,  KITAMURA YOSHIO ,  TAKEYARI YUKIO ,  IBUKA MAKOTO ,  YAMAMOTO SENJI

    IPC: B41B23/00 ,  G06T11/60 ,  H04N1/387 ,  H04N1/393 ,  B41L19/00

    Abstract: An information processing apparatus includes an image processing section for processing image and character information, a word processing section for processing character information, and a display section for displaying both the image and character information. The word processing section may be of a conventional type. The image processing section includes an image sensor which detects an image recorded on a document and produces an image signal in response thereto, a RAM for storing the image signal, a central processing unit for editing the image signal stored in RAM so as to erase, transfer, or reduce the size of at least a portion of the corresponding image and for storing the edited image signal in the RAM, and a printer for printing out the contents of the RAM. The display section includes a CRT for displaying both the character information generated by the word processing section and the image information detected by the image processing section. A bus control device connects the word processing section to the image processing section so that character information edited with the use of the CRT can be stored along with edited image information in the RAM, whereby the printer is adapted to print out both the edited character and image information stored in the RAM.

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