公开(公告)号：JP2002217408A

公开(公告)日：2002-08-02

申请号：JP2001006211

申请日：2001-01-15

Applicant: SONY CORP

Inventor： MORIYAMA ICHIRO

IPC: H01L29/78 ,  H01L21/265

Abstract: PROBLEM TO BE SOLVED: To accurately control impurity concentration at the end of a drain region in an MIS transistor with groove type gate electrode structure and to cope also with a shorter channel. SOLUTION: An element splitting area 2 is formed on a semiconductor substrate 1 to form a semiconductor region as a source area and a drain region in an element region, and then an interlayer insulation film 10 is formed on the entire surface of the substrate. An opening 11 is formed therein, and the interlayer insulation film 10 is etched through the opening 11, until the substrate 1 is exposed, and a groove 5 having a reverse-trapezoidal cross section is formed and then the semiconductor region is divided into a source region 3 and a drain region 4. After an insulation film 6 is formed on the bottom and sidewall of the groove 5, impurity ions are implanted in the direction inclining with respect to the main surface of the substrate 1, while using the interlayer insulation film 10 as a mask. Thus, a diffusion layer 9, whose impurity concentration is lower than the drain region 4, is formed integrally together with the drain region 4.

公开(公告)号：JPH0936225A

公开(公告)日：1997-02-07

申请号：JP18125995

申请日：1995-07-18

Applicant: SONY CORP

Inventor： MORIYAMA ICHIRO

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To prevent the misalignment between a conductive layer and a mask for forming contact hole so as to prevent the deterioration of contact section coverage and electrical reliability of a semiconductor device and the disconnection of wiring. SOLUTION: After a conductive film is formed on a base layer 4 composed of a semiconductor substrate 1, an insulating film 2 formed on the surface of the substrate 1, and a first wiring layer (first conductive layer) 3 formed on the film 2, conductive connecting sections 5 connected to the first wiring layer 3 are formed by patterning the conductive film. Then a first insulating film 6 is formed on the base layer 4 so as to cover the connecting sections 5 and the insulating film 6 is removed until the upper surfaces of the connecting section 5 are exposed. Thereafter, second wiring layers (second conductive layers) 7 which are connected to the exposed surfaces of the connecting sections 5 are formed on the first insulating film 6.

公开(公告)号：JPH08335629A

公开(公告)日：1996-12-17

申请号：JP14044795

申请日：1995-06-07

Applicant: SONY CORP

Inventor： MORIYAMA ICHIRO

IPC: H01L21/768

Abstract: PURPOSE: To realize the forming of an interlayer insulation film superior in reliability and the flattening of the surface thereof at low cost. CONSTITUTION: On a substrate (semiconductor substrate 11 having an insulating film 12) a interconnection 14 is formed. A dummy pattern 15 is formed with the same interconnection forming layer 13 as that of the interconnection 14 on other region except an interconnection forming region 15, side wall insulation films 18 and 19 are formed on the side walls of the pattern 15 and interconnection 14, then only the pattern 15 is removed, and insulation film (third insulation film 21) which covers the interconnection 14 and the insulation films 18 and 19 and forms voids 22 inside the insulation film 19. Then the surface of the film 21 is flattened.

公开(公告)号：JPH07106439A

公开(公告)日：1995-04-21

申请号：JP27004293

申请日：1993-10-01

Applicant: SONY CORP

Inventor： MORIYAMA ICHIRO

IPC: H01L27/112 ,  H01L21/8246

Abstract: PURPOSE:To increase the margin at the time of programming by decreasing the junction leakage current at a source-drain diffusion layer even when the programming is effected through ion implantation. CONSTITUTION:A memory cell is formed of transistors 43, 44 of SOT structure having an active layer of polysilicon 36 wherein the polysilicon 36 is formed shallower than a thickness when the impurity ions 25 being implanted for the purpose of programming reaches a peak concentration whereas a source-drain diffusion layer 42 is formed deeper than that depth. This structure inhibits occurrence of crystal defect in the source-drain layer 42 and since no junction is present on the bottom face of the source-drain diffusion layer 42, the junction leakage current is suppressed upon occurrence of crystal defect.

公开(公告)号：JPH05315605A

公开(公告)日：1993-11-26

申请号：JP14225292

申请日：1992-05-07

Applicant: SONY CORP

Inventor： MORIYAMA ICHIRO

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/784

Abstract: PURPOSE:To realize a MOS type semiconductor device suited to higher integration by providing a gate electrode made of a main gate electrode and a sub-gate made of a conductive material having a large work function difference for semiconductor substrate. CONSTITUTION:A gate insulation film 20 and a gate electrode 25 are laminated on the surface of semiconductor substrate; on the surface of semiconductor substrate 2 at both the sides of this, a source drain regions 28, 28 are formed, gate electrode 25 comprises a main gate electrode 24 and a sub-gate electrode 30, and the main gate electrode 24 is doped with N-type impurities. And the sub-gate electrode 30 is formed to a side wall shape at both the sides of the main gate electrode 24; since conductive impurities, the same as those of the main gate electrode are doped with a higher concentration, a work function difference is created for semiconductor substrate 2, and the work function difference of the sub-gate electrode 30 is higher than that of the main gate electrode. Thus, in MOS type semiconductor device 27, drop in threshold voltage due to short channel effect can be suppressed, and MOS transistor can be made thinner.

公开(公告)号：JPH06310684A

公开(公告)日：1994-11-04

申请号：JP12088493

申请日：1993-04-23

Applicant: SONY CORP

Inventor： MORIYAMA ICHIRO

IPC: H01L27/112 ,  H01L21/8246

Abstract: PURPOSE:To diminish a junction leak via the crystal defect in a diffused layer, even if an ion implantation for programming is performed. CONSTITUTION:The thickness of a polycrystalline Si film 14 being a gate electrode is increased or the gate electrode is formed of a high melting point metal film so that an ion implantation-stopping power is improved. Therefore, even if an ion implantation is performed under the condition that the peak impurity concentration for programming is positioned directly under the gate electrode in a channel region, a part (d), in which a crystal defect is generated in a region with a diffused layer 13 formed therein, is deeper than the junction depth (c) of the diffused layer 13.

公开(公告)号：JPH0621449A

公开(公告)日：1994-01-28

申请号：JP20311692

申请日：1992-07-06

Applicant: SONY CORP

Inventor： MORIYAMA ICHIRO

IPC: H01L27/08 ,  H01L29/78 ,  H01L29/784

Abstract: PURPOSE:To improve characteristics of a MOS-type transistor with a short channel while forming its channel part in a desired impurity concentration, by suppressing the redistribution of the impurities of its channel part through the process subjected to a temperature fall. CONSTITUTION:In a MOS-type transistor with a short channel, a gate 15 is formed on a semiconductor substrate 11 via a gate insulating film 14, and shallow diffusion layer regions 16, 17 are formed on the upper layers of the substrate 11, which are laid on both the sides of the gate 15, and insulating parts 18, 18 are formed on both the sides of the gate 15, and further, source.drain regions 19, 20, whose levels are nearly equal to the gate 15, are formed respectively on the regions 16, 17, and moreover, on the upper layers thereof, low resistance layers 21, 22 are formed respectively. Alternatively, in the transistor, on the upper layers of the substrate 11, which are laid on the oppsite sides of the insulating parts 18, 18 to the gate 15, the shallow diffusion layer regions 16, 17 are formed respectively, and further, on the upper layer of the substrate 11, an insulating layer is formed, and moreover, on this insulating layer, the sourece.drain regions 19, 20, whose levels are nearly equal to the gate 15, are so formed as to be connected respectively with the shallow diffusion layer regions 16, 17.

公开(公告)号：JPH10189718A

公开(公告)日：1998-07-21

申请号：JP34840796

申请日：1996-12-26

Applicant: SONY CORP

Inventor： MORIYAMA ICHIRO

IPC: H01L23/522 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacture thereof which enable formation of a fine multilayer interconnection being submicron or less without causing a problem on characteristics of an increase in electric resistance and a problem on the reliability of a phenomenon of electromigration even when an alignment error occurs. SOLUTION: An insulated gate type field effect transistor or the like is formed on a semiconductor substrate and an insulating film 1 being flattened is so formed as to cover this surface. A conductive part 3 formed on the insulating layer 1, a wiring layer 7 formed on an insulating layer 5 on the wiring layer 3 and a cylindrical wiring connecting part 9 formed in contact with the conductive part 3 and connecting the two layers 3 and 7 are provided. Since the wiring connecting part 9 is so formed as to pierce the wiring layer 7, the lateral side of the wiring layer 7 and that of the wiring connecting part 9 are in contact with each other. Accordingly, the electric connection of the wiring layer 7 and the wiring connecting part 9 is conducted on these lateral sides.

公开(公告)号：JPH09330976A

公开(公告)日：1997-12-22

申请号：JP17295196

申请日：1996-06-12

Applicant: SONY CORP

Inventor： MORIYAMA ICHIRO

IPC: H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method by which the occurrence of a provided via hole which occurs in the via hole of an interlayer insulating film constructed in a multilayered wiring structure can be prevented effectively. SOLUTION: When a via hole is formed in an interlayer insulating film composed of PTEOS-NSG(plasma TEOS-nondoped silicate glass) films 13 and 15 and an SOG film (spin on glass film 14, the via hole is not formed to an aluminum wiring layer 12 by one time of etching, but formed in two steps. In the first step, a via hole 18-1 is formed until the SOG film 14 is exposed in a first etching step and a via hole 18-2 is formed to the wiring layer 12 in a second etching step after coating the SOG film 14 with an acid-resistant thin film (PTEOS-NSG film 30). Since the conductive deposit which is produced by the etching does not adhere directly to the exposed part of the SOG film 14, the film 14 is protected front oxidation by the PTEOS-NSG film 30 during the resist ashing and organic cleaning processes which are performed for removing the deposit after the etching process.

公开(公告)号：JPH06268178A

公开(公告)日：1994-09-22

申请号：JP4849893

申请日：1993-03-10

Applicant: SONY CORP

Inventor： MORIYAMA ICHIRO

IPC: H01L21/265 ,  H01L21/8246 ,  H01L27/112

Abstract: PURPOSE:To enable sure impurity implantation and control of threshold value even if a depth from a surface of an upper layer film to a set region varies by setting ion implantation energy to position a concentration peak of impurities below a set region of a semiconductor substrate whereto impurities of a semiconductor substrate is to be introduced. CONSTITUTION:A gate oxide film 12 and a field oxide film 13 are formed in a p-type silicon substrate 11. After polysilicon is deposited, gate electrodes 14a to 14c, etc., are formed by patterning. Then, arsenic As of n-type impurities is implanted to form an impurity diffusion region 15 by using the gate electrode, etc., as a mask. A first layer insulation film 16 and a second layer insulation film 18 are formed as an upper layer film. Boron B of p-type impurities is implanted using resist 19 applied to the second layer insulation film 18 as a mask. This ion implantation is performed under the conditions that a concentration peak of impurities is located below a region of the silicon substrate 11 whereto impurities are introduced.