公开(公告)号：US20230185571A1

公开(公告)日：2023-06-15

申请号：US18048757

申请日：2022-10-21

Applicant: ST Microelectronics (Grenoble 2) SAS

Inventor： Valerie Assemat ,  Jeremy Ribeiro De Freitas ,  Edwin Hilkens ,  Isabelle Carnel

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F9/3001

Abstract: In an embodiment an integrated circuit includes a hardware calculator configured to calculate in parallel a first output component Yn−1 of a first rank n−1 and a second output component Yn of a second rank n which is higher than and consecutive to the first rank, according to the formula: Ym=Σk=0N−1bkxm−k, in a series of operations, wherein the hardware calculator includes a first calculation path dedicated to the first output component Yn−1, a second calculation path dedicated to the second output component Yn, wherein, for each operation, a first register is configured to contain a pair of first factors {xi, xi−1} corresponding to terms {bkxm−k}[k;k+1]m=n−1 of an operation in the first path, a second register is configured to contain a pair of second factors {bj, bj+1} corresponding to terms {bkxm−k}[k;k+1]m=n−1 of the operation in the first path, and a third register is configured to contain a pair of second factors {bj+2, bj+3} corresponding to terms {bkxm−k}[k+2;k+3]m=n−1 of the next operation in the first path.