公开(公告)号：CA2547050C

公开(公告)日：2009-12-22

申请号：CA2547050

申请日：2006-05-15

Applicant: STARKEY LAB INC

Inventor： WAHL JERRY ,  FAROOQI NEAZ ,  RICHARDSON GARRY

IPC: H03M1/12 ,  H03H17/02 ,  H03M1/06 ,  H03M3/02

Abstract: A low power analog-to-digital channel includes a decimation filter coupled t o a sigma-delta modulator. Various embodiments include a decimation filter including an output and a sigma-delta modulator coupled to the output of the decimation filter, where a clock frequency applied to the decimation filter is approximately a integral multiple of a sampling frequency of the sigma delta modulator. In an embodiment, the sigma-delta modulator includes one or more successive approximation converters. In an embodiment, the sigma delta modulator includes one or more area efficient integrators.

公开(公告)号：CA2547050A1

公开(公告)日：2006-11-19

申请号：CA2547050

申请日：2006-05-15

Applicant: STARKEY LAB INC

Inventor： RICHARDSON GARRY ,  FAROOQI NEAZ ,  WAHL JERRY

IPC: H03M1/12 ,  H03H17/02 ,  H03M1/06 ,  H03M3/02

Abstract: A low power analog-to-digital channel includes a decimation filter coupled t o a sigma-delta modulator. Various embodiments include a decimation filter including an output and a sigma-delta modulator coupled to the output of the decimation filter, where a clock frequency applied to the decimation filter is approximately a integral multiple of a sampling frequency of the sigma delta modulator. In an embodiment, the sigma-delta modulator includes one or more successive approximation converters. In an embodiment, the sigma delta modulator includes one or more area efficient integrators.