公开(公告)号：EP1603239B1

公开(公告)日：2012-10-24

申请号：EP05011771.2

申请日：2005-06-01

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Gupta, Nitin

IPC: H03K19/003

CPC classification number: H03K19/00315

公开(公告)号：EP1603239B8

公开(公告)日：2012-11-28

申请号：EP05011771.2

申请日：2005-06-01

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Gupta, Nitin

IPC: H03K19/003

CPC classification number: H03K19/00315

公开(公告)号：EP1603239A1

公开(公告)日：2005-12-07

申请号：EP05011771.2

申请日：2005-06-01

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Gupta, Nitin

IPC: H03K19/003

CPC classification number: H03K19/00315

Abstract: An voltage tolerant protection circuit for input buffer comprising a transmission gate circuit (11) receiving input from a pad for passing the input signal to the input of the input buffer, a control signal generator (12) connected between said transmission gate circuit (11) and the pad to provide a control signal (PMOSCTRL) for operating said transmission gate circuit (11), and an N-Well generation circuit (13) connected between the pad and said transmission gate circuit (11), and also connected to said control signal generator (12) for generating a bias signal (NWELL) for said transmission gate circuit (11) and said control signal generator (12). Thus, the present invention provides a voltage tolerant protection circuit that prevents electrical stress on transistors comprised within the transmission gate circuit (11) and the control signal generator (12), minimizes power supply consumption and transfers signals without any change in amplitude.

Abstract translation: 一种用于输入缓冲器的耐压保护电路，包括：传输门电路（11），接收来自焊盘的输入，用于将输入信号传递到输入缓冲器的输入;控制信号发生器（12），连接在所述传输门电路（11） 以及提供用于操作所述传输门电路（11）的控制信号（PMOSCTRL）的焊盘和连接在焊盘和所述传输门电路（11）之间的N阱产生电路（13），并且还连接到所述控制 信号发生器（12），用于产生用于所述传输门电路（11）和所述控制信号发生器（12）的偏置信号（NWELL）。 因此，本发明提供了一种耐电压保护电路，其防止在传输门电路（11）和控制信号发生器（12）内的晶体管的电应力，使电源消耗最小化并传输信号而没有任何幅度变化。