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1.发明授权An improved area efficient memory architecture with decoder self test and debug capability 有权改进的范围内高效的内存架构解码器自动测试和调试能力
公开(公告)号：EP1727156B1
公开(公告)日：2015-01-07
申请号：EP06114150.3
申请日：2006-05-18
Applicant: STMicroelectronics Pvt. Ltd.
Inventor： DUBEY, Prashant
IPC: G11C29/02
CPC classification number: G11C29/02 , G11C5/025 , G11C29/024 , G11C2029/1206
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2.发明公开An improved area efficient memory architecture with decoder self test and debug capability 有权Verbesserte bereichseffiziente Speicherarchitektur mit Dekoderautotest und Debug-Fähigkeit
公开(公告)号：EP1727156A2
公开(公告)日：2006-11-29
申请号：EP06114150.3
申请日：2006-05-18
Applicant: STMicroelectronics Pvt. Ltd
Inventor： DUBEY, Prashant
IPC: G11C29/02
CPC classification number: G11C29/02 , G11C5/025 , G11C29/024 , G11C2029/1206
Abstract: The invention provides an integrated test device thereby reducing external wiring congestion to the memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external BIST. Furthermore, the number of clock cycles required for the decoder testing for an N-address memory is reduced from 4N cycles to N clock cycles. Additionally, the access time for the memory is reduced as the test device is used as a pipelining device in normal operation mode.
Abstract translation: 本发明提供一种集成的测试装置，从而减少对存储器的外部布线拥塞。 集成测试设备提供单独的解码器测试和调试，以发现存储器中的特定错误。 该器件还有助于降低外部BIST测试的复杂性。 此外，N寻址存储器的解码器测试所需的时钟周期数从4N周期减少到N个时钟周期。 此外，随着测试设备在正常操作模式下用作流水线设备，存储器的访问时间减少。
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3.发明公开An improved area efficient memory architecture with decoder self test and debug capability 有权改进的范围内高效的内存架构解码器自动测试和调试能力
公开(公告)号：EP1727156A3
公开(公告)日：2008-04-09
申请号：EP06114150.3
申请日：2006-05-18
Applicant: STMicroelectronics Pvt. Ltd.
Inventor： DUBEY, Prashant
IPC: G11C29/02
CPC classification number: G11C29/02 , G11C5/025 , G11C29/024 , G11C2029/1206
Abstract: The invention provides an integrated test device thereby reducing external wiring congestion to the memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external BIST. Furthermore, the number of clock cycles required for the decoder testing for an N-address memory is reduced from 4N cycles to N clock cycles. Additionally, the access time for the memory is reduced as the test device is used as a pipelining device in normal operation mode.
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