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公开(公告)号：EP4319039A9
公开(公告)日：2024-03-20
申请号：EP23186442.2
申请日：2023-07-19
Applicant: STMicroelectronics S.r.l.
Inventor： QUARTIROLI, Matteo , MECCHIA, Alessandro , PESENTI, Paolo
Abstract: A synchronizing digital device includes a reference input (26a), receiving a reference clock signal (CKB) at a reference clock frequency (F CKB ); an output (17); a local oscillator (14), providing a local clock signal (CKJ) having a local clock frequency (F CKJ ); a digital signal source (15), based on the local clock signal (CKJ) and providing digital signals (SD); and a synchronization stage (18). The synchronization stage (18) is based on the local clock signal (CKJ) and includes: a resampler (22), arranged between the digital signal source (15) and the output (17) and configured to make available resampled digital signals (SDRS), obtained by taking samples of the digital signals (SD) with a resampling frequency (F RS ); and a sigma-delta modulator (20) configured to cause the generation of a resampling signal (CKF) modulated on average at the resampling frequency (F RS ) as a function of the reference clock signal (CKB) and to control the resampler (22) through the resampling signal (CKF) .
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公开(公告)号：EP4067825A1
公开(公告)日：2022-10-05
申请号：EP22165644.0
申请日：2022-03-30
Applicant: STMicroelectronics S.r.l.
Inventor： QUARTIROLI, Matteo , MECCHIA, Alessandro , MAESTRI, Laura
Abstract: The sensor (5) is configured to provide a digital output signal (S O ) and has a digital detector (13), which is configured to detect a physical quantity and generate a conditioned digital signal (S D ) indicative of the detected physical quantity; and a rate modification stage (15), configured to receive the conditioned digital signal and a group of parameters (K), the group of parameters comprising an interpolation factor (I 1 ) and a downsampling factor (D 1 , M), and to provide the digital output signal. The rate modification stage has an interpolator (36) and a decimation element (40, 60). The interpolator is configured to receive and to upsample the conditioned digital signal based on the interpolation factor and to provide an interpolated signal (S D,int ). The decimation element is configured to downsample the interpolated signal based on the downsampling factor, thereby generating the digital output signal.
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公开(公告)号：EP4319039A1
公开(公告)日：2024-02-07
申请号：EP23186442.2
申请日：2023-07-19
Applicant: STMicroelectronics S.r.l.
Inventor： QUARTIROLI, Matteo , MECCHIA, Alessandro , PESENTI, Paolo
Abstract: A synchronizing digital device includes a reference input (26a), receiving a reference clock signal (CKB) at a reference clock frequency (F CKB ); an output (17); a local oscillator (14), providing a local clock signal (CKJ) having a local clock frequency (F CKJ ); a digital signal source (15), based on the local clock signal (CKJ) and providing digital signals (SD); and a synchronization stage (18). The synchronization stage (18) is based on the local clock signal (CKJ) and includes: a resampler (22), arranged between the digital signal source (15) and the output (17) and configured to make available resampled digital signals (SDRS), obtained by taking samples of the digital signals (SD) with a resampling frequency (F RS ); and a sigma-delta modulator (20) configured to cause the generation of a resampling signal (CKF) modulated on average at the resampling frequency (F RS ) as a function of the reference clock signal (CKB) and to control the resampler (22) through the resampling signal (CKF) .
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