公开(公告)号：EP3859975A1

公开(公告)日：2021-08-04

申请号：EP21151784.2

申请日：2021-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： MODAFFARI, Roberto ,  PESENTI, Paolo ,  NICOLLINI, Germano

IPC: H03M3/02 ,  H03M3/04

Abstract: An excess loop delay (ELD) compensation network (120) for a sigma-delta modulator (10) comprises a derivative circuit (1202) configured to receive a weighed ( k 0C ) replica of the integrated signal ( y 1 ( t )) from the input integrator circuit (201) of the modulator and produce therefrom a derivative signal as well as a sign-reversal circuit (1204, 1206a, 1206b, φ C , φ C (neg)) configured to alternately reverse the sign of the derivative signal over subsequent time intervals of a duration half the sampling period (Ts) of the output quantizer circuit (A/D) of the modulator. A further integrator circuit (1208) is provided to integrate the derivative signal having alternately reversed sign along with an excess loop delay ( Z -τ ) compensation node (303) configured to inject into the signal propagation path (201, 302, 202, 303) towards the output quantizer circuit (A/D) an excess loop delay ( Z -τ ) compensation signal comprising the derivative signal after integration at the least one further integrator circuit (1208). Alternative embodiments may contemplate injecting the derivative signal into the signal propagation path towards the quantizer circuit (A/D) before integration of the derivative signal.

公开(公告)号：EP4044431A1

公开(公告)日：2022-08-17

申请号：EP22153004.1

申请日：2022-01-24

Applicant: STMicroelectronics S.r.l.

Inventor： MODAFFARI, Roberto ,  NICOLLINI, Germano

IPC: H03F3/45

Abstract: A circuit (50; 70) for startup of a multi-stage amplifier circuit (10) comprising a cascade of differential stages having at least a first differential stage (M 1 , M 2 ), the circuit (50; 70) comprising: a pair of input nodes (V SUp , V SUn ) and at least two output nodes (V 1p , V 1 ; V CP1 , V CP2 , V CN1 , V CN2 ) configured to be coupled to the multi-stage amplifier circuit (10), a startup differential stage comprising a differential pair of transistors (M SU1 , M SU2 ) having respective control terminals coupled to the pair of input nodes (V SUp , V SUn ), each transistor (M sui ) in the differential pair of transistors (M sui , M SU2 ) having a respective current path therethrough between a respective output node (V 1p , V 1n , V CP1 , V CP2 ) in the at least two output nodes (V 1p , V 1n ; V CP1 , V CP2 , V CN1 , V CN2 ), and a common source terminal, the startup differential stage configured to sense (M sui , M SU2 ) a common mode voltage drop at the first differential stage (M 1 , M 2 ) of the multi-stage amplifier circuit (10), current mirror circuitry (M SU3 , M SU4 , M SU5 ) comprising a plurality of transistors in a current mirror arrangement coupled to the common terminal of the first differential pair of transistors (M sui , M SU2 ) and having two output nodes in the at least two output nodes wherein at least two output nodes are configured to be coupled to the first differential stage (M 1 , M 2 ) of the multi-stage amplifier circuit (10)