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公开(公告)号：EP4319039A9
公开(公告)日：2024-03-20
申请号：EP23186442.2
申请日：2023-07-19
Applicant: STMicroelectronics S.r.l.
Inventor： QUARTIROLI, Matteo , MECCHIA, Alessandro , PESENTI, Paolo
Abstract: A synchronizing digital device includes a reference input (26a), receiving a reference clock signal (CKB) at a reference clock frequency (F CKB ); an output (17); a local oscillator (14), providing a local clock signal (CKJ) having a local clock frequency (F CKJ ); a digital signal source (15), based on the local clock signal (CKJ) and providing digital signals (SD); and a synchronization stage (18). The synchronization stage (18) is based on the local clock signal (CKJ) and includes: a resampler (22), arranged between the digital signal source (15) and the output (17) and configured to make available resampled digital signals (SDRS), obtained by taking samples of the digital signals (SD) with a resampling frequency (F RS ); and a sigma-delta modulator (20) configured to cause the generation of a resampling signal (CKF) modulated on average at the resampling frequency (F RS ) as a function of the reference clock signal (CKB) and to control the resampler (22) through the resampling signal (CKF) .
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公开(公告)号：EP3859975A1
公开(公告)日：2021-08-04
申请号：EP21151784.2
申请日：2021-01-15
Applicant: STMicroelectronics S.r.l.
Inventor： MODAFFARI, Roberto , PESENTI, Paolo , NICOLLINI, Germano
Abstract: An excess loop delay (ELD) compensation network (120) for a sigma-delta modulator (10) comprises a derivative circuit (1202) configured to receive a weighed ( k 0C ) replica of the integrated signal ( y 1 ( t )) from the input integrator circuit (201) of the modulator and produce therefrom a derivative signal as well as a sign-reversal circuit (1204, 1206a, 1206b, φ C , φ C (neg)) configured to alternately reverse the sign of the derivative signal over subsequent time intervals of a duration half the sampling period (Ts) of the output quantizer circuit (A/D) of the modulator. A further integrator circuit (1208) is provided to integrate the derivative signal having alternately reversed sign along with an excess loop delay ( Z -τ ) compensation node (303) configured to inject into the signal propagation path (201, 302, 202, 303) towards the output quantizer circuit (A/D) an excess loop delay ( Z -τ ) compensation signal comprising the derivative signal after integration at the least one further integrator circuit (1208). Alternative embodiments may contemplate injecting the derivative signal into the signal propagation path towards the quantizer circuit (A/D) before integration of the derivative signal.
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公开(公告)号：EP4319039A1
公开(公告)日：2024-02-07
申请号：EP23186442.2
申请日：2023-07-19
Applicant: STMicroelectronics S.r.l.
Inventor： QUARTIROLI, Matteo , MECCHIA, Alessandro , PESENTI, Paolo
Abstract: A synchronizing digital device includes a reference input (26a), receiving a reference clock signal (CKB) at a reference clock frequency (F CKB ); an output (17); a local oscillator (14), providing a local clock signal (CKJ) having a local clock frequency (F CKJ ); a digital signal source (15), based on the local clock signal (CKJ) and providing digital signals (SD); and a synchronization stage (18). The synchronization stage (18) is based on the local clock signal (CKJ) and includes: a resampler (22), arranged between the digital signal source (15) and the output (17) and configured to make available resampled digital signals (SDRS), obtained by taking samples of the digital signals (SD) with a resampling frequency (F RS ); and a sigma-delta modulator (20) configured to cause the generation of a resampling signal (CKF) modulated on average at the resampling frequency (F RS ) as a function of the reference clock signal (CKB) and to control the resampler (22) through the resampling signal (CKF) .
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