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公开(公告)号：EP4319039A9
公开(公告)日：2024-03-20
申请号：EP23186442.2
申请日：2023-07-19
Applicant: STMicroelectronics S.r.l.
Inventor： QUARTIROLI, Matteo , MECCHIA, Alessandro , PESENTI, Paolo
Abstract: A synchronizing digital device includes a reference input (26a), receiving a reference clock signal (CKB) at a reference clock frequency (F CKB ); an output (17); a local oscillator (14), providing a local clock signal (CKJ) having a local clock frequency (F CKJ ); a digital signal source (15), based on the local clock signal (CKJ) and providing digital signals (SD); and a synchronization stage (18). The synchronization stage (18) is based on the local clock signal (CKJ) and includes: a resampler (22), arranged between the digital signal source (15) and the output (17) and configured to make available resampled digital signals (SDRS), obtained by taking samples of the digital signals (SD) with a resampling frequency (F RS ); and a sigma-delta modulator (20) configured to cause the generation of a resampling signal (CKF) modulated on average at the resampling frequency (F RS ) as a function of the reference clock signal (CKB) and to control the resampler (22) through the resampling signal (CKF) .
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公开(公告)号：EP4067830A1
公开(公告)日：2022-10-05
申请号：EP22165663.0
申请日：2022-03-30
Applicant: STMicroelectronics S.r.l.
Inventor： QUARTIROLI, Matteo , ROSINGANA, Paolo
IPC: G01D21/00
Abstract: The integrated sensor (5A-5C) is configured to receive a frequency-indication signal (EXT_REF) and to supply an output digital signal (S O ) formed by a plurality of samples. The integrated sensor has a digital detector (48), which detects a physical quantity and generates a discrete detection signal (S D ) indicative of the detected physical quantity; an output timing regulation block (80, 83), which receives the frequency-indication signal and a set of local reference signals (CLK, INT_REF) and generates a trigger signal (OUT_TRG) as a function of the frequency-indication signal and of the set of local reference signals; and an output stage (49), which receives the discrete detection signal and the trigger signal (OUT_TRG) and supplies the digital output signal (S O ) and a locking signal (EXT_REF, INT_REF). The output stage (49) supplies a sample of the discrete detection signal in response to the reception of the trigger signal, thus generating the digital output signal, and supplies the locking signal in response to the reception of the trigger signal. The locking signal is temporally aligned with the digital output signal.
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Patent Agency Ranking
公开(公告)号：EP4407277A1
公开(公告)日：2024-07-31
申请号：EP24152547.6
申请日：2024-01-18
Applicant: STMicroelectronics S.r.l.
Inventor： MAGNANI, Alessandro , QUARTIROLI, Matteo , RIZZO PIAZZA RONCORONI, Alessandra Maria , ROSINGANA, Paolo
IPC: G01C19/5776 , G01C21/12
CPC classification number: G01C19/5776 , G01C21/12
Abstract: A device includes one or more inertial sensors and fusion circuitry coupled to the one or more inertial sensors. The inertial sensors, in operation, generate inertial sensor data with respect to a plurality of axes of movement. The fusion circuitry, in a polar fusion mode of operation, applies a plurality of polar rotation operations to the generated inertial sensor data to rotate the generated inertial sensor data onto an axis of the plurality of axes of movement. A fused data signal is generated based on a result of the plurality of polar rotation operations. The plurality of inertial sensors may include bone-conduction sensors.
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公开(公告)号：EP4067825A1
公开(公告)日：2022-10-05
申请号：EP22165644.0
申请日：2022-03-30
Applicant: STMicroelectronics S.r.l.
Inventor： QUARTIROLI, Matteo , MECCHIA, Alessandro , MAESTRI, Laura
Abstract: The sensor (5) is configured to provide a digital output signal (S O ) and has a digital detector (13), which is configured to detect a physical quantity and generate a conditioned digital signal (S D ) indicative of the detected physical quantity; and a rate modification stage (15), configured to receive the conditioned digital signal and a group of parameters (K), the group of parameters comprising an interpolation factor (I 1 ) and a downsampling factor (D 1 , M), and to provide the digital output signal. The rate modification stage has an interpolator (36) and a decimation element (40, 60). The interpolator is configured to receive and to upsample the conditioned digital signal based on the interpolation factor and to provide an interpolated signal (S D,int ). The decimation element is configured to downsample the interpolated signal based on the downsampling factor, thereby generating the digital output signal.
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公开(公告)号：EP4319039A1
公开(公告)日：2024-02-07
申请号：EP23186442.2
申请日：2023-07-19
Applicant: STMicroelectronics S.r.l.
Inventor： QUARTIROLI, Matteo , MECCHIA, Alessandro , PESENTI, Paolo
Abstract: A synchronizing digital device includes a reference input (26a), receiving a reference clock signal (CKB) at a reference clock frequency (F CKB ); an output (17); a local oscillator (14), providing a local clock signal (CKJ) having a local clock frequency (F CKJ ); a digital signal source (15), based on the local clock signal (CKJ) and providing digital signals (SD); and a synchronization stage (18). The synchronization stage (18) is based on the local clock signal (CKJ) and includes: a resampler (22), arranged between the digital signal source (15) and the output (17) and configured to make available resampled digital signals (SDRS), obtained by taking samples of the digital signals (SD) with a resampling frequency (F RS ); and a sigma-delta modulator (20) configured to cause the generation of a resampling signal (CKF) modulated on average at the resampling frequency (F RS ) as a function of the reference clock signal (CKB) and to control the resampler (22) through the resampling signal (CKF) .
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公开(公告)号：EP4332783A1
公开(公告)日：2024-03-06
申请号：EP23191304.7
申请日：2023-08-14
Applicant: STMicroelectronics S.r.l.
IPC: G06F13/372 , G06F13/40
Abstract: An integrated circuit includes a control circuit, a primary sensor device coupled to the control circuit, and a plurality of groups of secondary sensor devices coupled to the primary sensor device. The primary sensor device receives a master clock signal from the control device and outputs, to each group of secondary sensor devices, a respective secondary clock signal with a frequency lower than the primary clock signal. The primary sensor device generates primary sensor data. The primary sensor device receives secondary sensor data from each group of secondary sensor devices. The primary sensor device combines the primary sensor data and all of the secondary sensor data into a sensor data stream with a time division-multiplexing scheme and outputs the sensor data stream to the control circuit.
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公开(公告)号：EP4084419A1
公开(公告)日：2022-11-02
申请号：EP22168201.6
申请日：2022-04-13
Applicant: STMicroelectronics S.r.l.
Inventor： RIZZO PIAZZA RONCORONI, Alessandra Maria , QUARTIROLI, Matteo , BASSOLI, Rossella , BALDRIGHI, Paola
IPC: H04L12/403
Abstract: The present disclosure is directed to a device (10) and method for generating and transmitting a TDM signal including both raw data and processed data. The device includes a sensor (18) having a time division multiplexing (TDM) interface (24). The TDM interface (24) transmits both raw data and processed data in a single TDM signal by reserving one or more slots inside a TDM frame for transmission of the processed data. The sensor (18) also embeds additional information inside a data stream of raw data by repurposing one or more of values of the raw data as an exception code, flag, or another type of notification. The device (10) is also enabled to transmit data, and disabled when not in use in order to conserve power.
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