公开(公告)号：EP3339868A1

公开(公告)日：2018-06-27

申请号：EP18151529.7

申请日：2008-12-19

Applicant: STMicroelectronics Srl

Inventor： PAGANI, Alberto

IPC: G01R1/073

CPC classification number: G01R31/2889 ,  B62M25/04 ,  G01R1/0491 ,  G01R1/06727 ,  G01R1/07342

Abstract: A probe card adapted for testing at least one integrated circuit integrated on corresponding at least one die of a semiconductor material wafer, the probe card including a board adapted for the coupling to a tester apparatus, and a plurality of probes coupled to the said board, wherein the probe card comprises a plurality of replaceable elementary units, each one comprising at least one of said probes for contacting externally-accessible terminals of an integrated circuit under test, the plurality of replaceable elementary units being arranged so as to correspond to an arrangement of at least one die on the semiconductor material wafer containing integrated circuits to be tested.

公开(公告)号：EP2324499B1

公开(公告)日：2012-01-18

申请号：EP09777658.7

申请日：2009-08-05

Applicant: STMicroelectronics Srl

Inventor： PAGANI, Alberto

IPC: H01L23/58 ,  G01R31/28

CPC classification number: H01L22/32 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a circuit architecture for the parallel supplying of power during an electric or electromagnetic testing, such as EMWS or EWS or WLBI testing, of a plurality of electronic devices (2) each integrated on a same semiconductor wafer (1) wherein the electronic devices (1) are neatly provided on the semiconductor wafer (1) through integration techniques and have edges (5) bounded by separation scribe lines (7). Advantageously according to the invention, the circuit architecture comprises: - at least one conductive grid (4), interconnecting at least one group of the electronic devices (2) and having a portion being external (14) to the devices of the group and a portion being internal (13) to the devices of the group; the external portion (14) of the conductive grid (4) being extended also along the separation scribe lines (7); the internal portion (13) being extended within at least a part of the devices of the group; interconnection pads (6) between the external portion (14) and the internal portion (13) of the conductive grid (4) being provided on at least a part of the devices of the group, the interconnection pads (6) forming, along with the internal and external portions, power supply lines which are common to different electronic devices (2) of the group.

公开(公告)号：EP2347310B1

公开(公告)日：2014-05-21

申请号：EP08875796.8

申请日：2008-10-22

Applicant: STMicroelectronics (Grenoble) SAS ,  STMicroelectronics Srl

Inventor： TENUCCI, Sergio ,  PAGANI, Alberto ,  SPINETTA, Marco ,  RANCHOUX, Bernard

IPC: G05B19/418 ,  G01R31/28

CPC classification number: G05B19/41875 ,  G01R31/2894 ,  Y02P90/22 ,  Y02P90/86

公开(公告)号：EP2235546A1

公开(公告)日：2010-10-06

申请号：EP08863657.6

申请日：2008-12-19

Applicant: STMicroelectronics Srl

Inventor： PAGANI, Alberto

IPC: G01R1/073

CPC classification number: G01R31/2889 ,  B62M25/04 ,  G01R1/0491 ,  G01R1/06727 ,  G01R1/07342

Abstract: A probe card is adapted for testing at least one integrated circuit that integrated on a corresponding at least one die of a semiconductor material wafer. The probe card includes a board adapted for the coupling to a tester apparatus. Several probes are coupled to the board. The probe card includes replaceable elementary units, wherein each unit includes at least one probe for contacting externally-accessible terminals of an integrated circuit under test. The replaceable elementary units are arranged so as to correspond to an arrangement of at least one die on the semiconductor material wafer containing integrated circuits to be tested.

Abstract translation: 探针卡适于测试集成在半导体材料晶片的相应的至少一个管芯上的至少一个集成电路。 探针卡包括适于耦合到测试仪器的板。 几个探头耦合到电路板。 探针卡包括可替换的基本单元，其中每个单元包括用于接触被测集成电路的外部可接近端子的至少一个探针。 可替换的基本单元布置成对应于包含待测试的集成电路的半导体材料晶片上的至少一个管芯的布置。

公开(公告)号：EP2324499A1

公开(公告)日：2011-05-25

申请号：EP09777658.7

申请日：2009-08-05

Applicant: STMicroelectronics Srl

Inventor： PAGANI, Alberto

IPC: H01L23/58 ,  G01R31/28

CPC classification number: H01L22/32 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a circuit architecture for the parallel supplying of power during an electric or electromagnetic testing, such as EMWS or EWS or WLBI testing, of a plurality of electronic devices (2) each integrated on a same semiconductor wafer (1) wherein the electronic devices (1) are neatly provided on the semiconductor wafer (1) through integration techniques and have edges (5) bounded by separation scribe lines (7). Advantageously according to the invention, the circuit architecture comprises: - at least one conductive grid (4), interconnecting at least one group of the electronic devices (2) and having a portion being external (14) to the devices of the group and a portion being internal (13) to the devices of the group; the external portion (14) of the conductive grid (4) being extended also along the separation scribe lines (7); the internal portion (13) being extended within at least a part of the devices of the group; interconnection pads (6) between the external portion (14) and the internal portion (13) of the conductive grid (4) being provided on at least a part of the devices of the group, the interconnection pads (6) forming, along with the internal and external portions, power supply lines which are common to different electronic devices (2) of the group.