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公开(公告)号:JP2000330258A
公开(公告)日:2000-11-30
申请号:JP13983099
申请日:1999-05-20
Applicant: UNITED MICROELECTRONICS CORP
Inventor: RIN KINRYU
IPC: H01L21/027 , G03F1/36 , G03F1/68 , G03F1/08
Abstract: PROBLEM TO BE SOLVED: To obtain a method for correcting optical proximity. SOLUTION: Main patterns 300 having critical dimensions are supplied. When the critical dimensions are a first reference value or below the value, serifs 304 (projecting patterns for correction)/hammer heads (hammer-like patterns for correction) are added to the main patterns 300. When the critical dimensions are a second reference value smaller than the first reference value or below the value, auxiliary patterns 302 are added to the main patterns 300. The corrected patterns are transferred onto the layer on a wafer with high fidelity.
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公开(公告)号:JP2000331903A
公开(公告)日:2000-11-30
申请号:JP13100499
申请日:1999-05-12
Applicant: UNITED MICROELECTRONICS CORP
Inventor: RIN KINRYU , KO YOSHIN
IPC: H01L21/027 , H01L27/10
Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a pattern equipped with a series of logics and storage circuits. SOLUTION: In a method for simultaneously forming patterns equipped with a logic circuit and a memory circuit, a wafer on which a photoresist layer is already formed is arranged, the photoresist layer is covered with a mask, and the mask covers an opaque block and a pattern block. The first exposure is advanced, the pattern of the mask is formed on the photoresist layer, the mask is removed, and the photoresist layer is covered by one mask. Then, the second exposure is advanced, and the other pattern is formed on the photoresist layer, and the second mask is removed. Thus, the pattern defined on the photoresist layer can be obtained with a satisfactory analytic level, and the quality of a product can be ensured.
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公开(公告)号:JP2000305245A
公开(公告)日:2000-11-02
申请号:JP10182199
申请日:1999-04-08
Applicant: UNITED MICROELECTRONICS CORP
Inventor: RIN KINRYU , KO YOSHIN
Abstract: PROBLEM TO BE SOLVED: To provide a strong phase-shift mask in which the production cost and cycle time is reduced and unbalance in strength is lowered by forming specified third depth and fourth depth, respectively, in a mask substrate by penetrating a first opening part and second opening part of a phase-shift layer. SOLUTION: A first opening part and second opening part are formed in a phase-shift layer 402 by patterning for exposing part of a mask substrate 400. Thereafter the mask substrate 400 is etched along the first opening part to a first depth having a phase shift of 90 deg. in the second opening part. Further, the mask substrate 400 is again etched along the first opening part to a second depth having a phase shift of 180 deg. in the second opening part. Then, an etching process is simultaneously carried out along the first opening part and second opening part, thereby a third depth s" of the first opening part 406 c and a fourth depth r of the second opening part 408 c, each having phase shift of 180 deg., can be obtained.
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公开(公告)号:JP2000206672A
公开(公告)日:2000-07-28
申请号:JP828299
申请日:1999-01-14
Applicant: UNITED MICROELECTRONICS CORP
Inventor: RIN KINRYU , KO YOSHIN
Abstract: PROBLEM TO BE SOLVED: To provide a dual photomask used in photolithography in the case of producing an integrated circuit and capable of performing double exposure operation on a semiconductor wafer without mask tooling. SOLUTION: This dual photomask 10 is equipped with a reticle glass plate 12 where a phase shift mask(PSM) chrome area 14 and a binary (BIN) chrome area 16 are adjacently arranged. When the photomask 10 is used, it is shifted between two previously decided positions that a pattern from the area 16 can be transferred to a wafer at the first position and the pattern from the area 14 can be transferred at other position. An exposure scanner is used to expose the wafer through the photomask 10. By this photomask 10, a defect such as the positional deviation of pattern transfer occurring because two masks are used in the case of the conventional technique is eliminated, further yield is improved and the production cost of the wafer is reduced.
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公开(公告)号:JP2001042501A
公开(公告)日:2001-02-16
申请号:JP20464099
申请日:1999-07-19
Applicant: UNITED MICROELECTRONICS CORP
Inventor: RIN KINRYU , KO YOSHIN
IPC: H01L21/027 , G03F1/36 , G03F1/68 , G03F1/08
Abstract: PROBLEM TO BE SOLVED: To obtain specified fidelity and to reduce the production cost by combining a part of a binary mask curve and a part of a phase shift mask curve to produce an optical characteristic curve and forming a corrected pattern of the original pattern based on the optical characteristic curve. SOLUTION: A binary mask curve (b) showing the relation of the critical dimension (x), and a phase shift mask curve (a) showing the relation of the critical dimension (x) between a corrected pattern and the original pattern are prepared. The critical value of the critical dimension x in the original pattern is selected. Then a part of the binary mask curve (b) corresponding to the region of the critical dimension (x) the original pattern larger than the critical value, and a part of the phase shift mask curve (a) corresponding to the region of the critical dimension (x) of the original pattern smaller than the critical value are combined to produce the optical characteristic curve. The corrected pattern of the original pattern is formed on the photomask based on the optical characteristic curve.
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