公开(公告)号：WO2008112673A2

公开(公告)日：2008-09-18

申请号：PCT/US2008056478

申请日：2008-03-11

Applicant: TOKYO ELECTRON LTD ,  TOKYO ELECTRON AMERICA INC ,  SUNDARARAJAN RADHA ,  CHEN LEE ,  FUNK MERRITT

Inventor： SUNDARARAJAN RADHA ,  CHEN LEE ,  FUNK MERRITT

IPC: H01L21/00 ,  H01L21/687

CPC classification number: H01L21/68735 ,  C23C16/4586 ,  C23C16/466 ,  H01L21/67069 ,  H01L21/67248 ,  H01L21/68714

Abstract: Control of radial or non-radial temperature distribution is controlled across a substrate during processing to compensate for non-uniform effects, including non-uniformities arising from system or process. Temperature is controlled, preferably dynamically, by flowing backside gas differently across different areas on a wafer supporting chuck (substrate support table 20, 20a) to vary heat conduction across the wafer. Ports (26, 26a) in the support table (20, 20a) are grouped, and gas to or from the groups is separately controlled by different valves (32) responsive to a controller (35) that controls gas pressure in each of the areas to spatially and preferably dynamically control wafer temperature to compensate for system and process non-uniformities. Wafer deformation is affected by separately controlling the pressure of the backside gas at different ports (26, 26a) to control the local force exerted on the backside of the substrate, by separately dynamically controlling valves (32) affecting gas flow to a port (26, 26a) and ports (26, 26a) surrounding said port (26, 26a).

Abstract translation: 径向或非径向温度分布的控制在处理过程中跨越衬底进行控制，以补偿不均匀的影响，包括由系统或过程产生的不均匀性。 通过在晶片支撑卡盘（衬底支撑台20,20a）上的不同区域上不同地流动背面气体来改变温度，优选动态地改变，以改变横跨晶片的热传导。 支撑台（20,20a）中的端口（26,26a）被分组，并且响应于控制器（35），单独地由不同的阀（32）控制到组或从组的气体，控制器控制每个区域中的气体压力 在空间上优选地动态地控制晶片温度以补偿系统和工艺的不均匀性。 通过分别控制不同端口（26,2b）处的背侧气体的压力来控制施加在基板的背面上的局部力，通过分别动态地控制影响到端口（26）的气体流动的阀（32）来影响晶片变形 ，26a）和围绕所述端口（26,2a）的端口（26,26a）。

公开(公告)号：WO2008067013A3

公开(公告)日：2008-09-04

申请号：PCT/US2007079133

申请日：2007-09-21

Applicant: A10 NETWORKS INC ,  CHEN LEE ,  CHIONG JOHN ,  WANG XIN

Inventor： CHEN LEE ,  CHIONG JOHN ,  WANG XIN

IPC: G06F9/00

CPC classification number: H04L63/102 ,  H04L12/66 ,  H04L29/06 ,  H04L61/6022 ,  H04L61/6068 ,  H04L63/02 ,  H04L63/0281 ,  H04L63/04 ,  H04L63/08 ,  H04L63/0853 ,  H04L63/10 ,  H04L63/30 ,  H04L63/308 ,  H04L65/1003 ,  H04L65/1006 ,  H04L65/1069 ,  H04L65/4007 ,  H04L67/14 ,  H04L67/141 ,  H04L67/146

Abstract: The inventive system includes a host, a network including a security gateway, and a public application. Established are an access session between the network and the host and an application session between the public application and the network. An application session record is created for the application session, and includes the user's public user identity used to access the public application, the user's private user identity used to access the network, a host identity, and an application session time. To determine the private user identity for the application session, the security gateway sends a query with the host identity and the application session time. These are compared with the host identity and access session time in an access session record. If they match, then the private user identity in the access session record is returned, and it is stored as the private user identity in the application session record.

Abstract translation: 本发明的系统包括主机，包括安全网关的网络和公共应用。 建立在网络和主机之间的访问会话以及公共应用程序和网络之间的应用程序会话。 为应用会话创建应用会话记录，并且包括用于访问公共应用的用户的公共用户标识，用于访问网络的用户的私有用户标识，主机标识和应用会话时间。 为了确定应用程序会话的私有用户身份，安全网关发送具有主机标识和应用程序会话时间的查询。 这些与访问会话记录中的主机身份和访问会话时间进行比较。 如果匹配，则返回访问会话记录中的私有用户身份，并将其作为私有用户身份存储在应用程序会话记录中。

公开(公告)号：WO2008021609A1

公开(公告)日：2008-02-21

申请号：PCT/US2007/070375

申请日：2007-06-05

Applicant: TOKYO ELECTRON LIMITED ,  VENTZEK, Peter, L.G. ,  CHEN, Lee ,  KOSHIISHI, Akira ,  SAWADA, Ikuo

Inventor： VENTZEK, Peter, L.G. ,  CHEN, Lee ,  KOSHIISHI, Akira ,  SAWADA, Ikuo

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/0273 ,  G03F7/40 ,  H01J37/32082 ,  H01J37/3233 ,  H01L21/0337 ,  H01L21/31144

Abstract: A method of pre-treating a mask layer prior to etching an underlying thin film is described. A thin film, such as a dielectric film, is etched using plasma that is enhanced with a ballistic electron beam. In order to reduce the loss of pattern definition, such as line edge roughness effects, the mask layer is treated with an oxygen-containing plasma or halogen-containing plasma or a noble gas plasma or a combination of two or more thereof prior to proceeding with the etching process.

Abstract translation: 描述了在蚀刻下面的薄膜之前对掩模层进行预处理的方法。 使用通过弹道电子束增强的等离子体蚀刻诸如电介质膜的薄膜。 为了减少图案定义的损失，例如线边缘粗糙度效应，在进行处理之前，用含氧等离子体或含卤素的等离子体或惰性气体等离子体或其两种或更多种的组合处理掩模层 蚀刻工艺。

公开(公告)号：WO2007037976A3

公开(公告)日：2008-01-03

申请号：PCT/US2006035452

申请日：2006-09-12

Applicant: AGILE RF INC ,  CHEN LEE-YIN V

Inventor： CHEN LEE-YIN V

IPC: H01L31/062

CPC classification number: H01L28/57 ,  H01L28/65

Abstract: Ferroelectric thin film devices including a passivation structure to reduce or control a leakage path between two electrodes and along an interface between a ferroelectric thin film layer and a passivation layer are described. Methods for fabricating such devices are also disclosed. The passivation structure includes a first passivation layer (140, Fig. 2) that includes an opening (205) exposing a portion of the ferroelectric thin film layer (125) allowing a second passivation layer (145) to contact the thin film layer (125) through the opening. In an exemplary embodiment, the opening is a rectangular ring (505, Fig. 6D) surrounding an active region of a capacitor. In another exemplary embodiment, the second passivation layer also contacts the second electrode, a portion of which is also exposed through the opening. In another exemplary embodiment, current flows along the interface between the thin film layer and the passivation layer in an integrated resistor (975, Fig. 9A).

Abstract translation: 描述了包括钝化结构以减少或控制两个电极之间以及沿着铁电薄膜层和钝化层之间的界面的泄漏路径的铁电薄膜器件。 还公开了制造这种装置的方法。 钝化结构包括第一钝化层（140，图2），其包括暴露铁电薄膜层（125）的一部分的开口（205），允许第二钝化层（145）接触薄膜层 ）通过开口。 在示例性实施例中，开口是围绕电容器的有源区域的矩形环（图6D中的505）。 在另一示例性实施例中，第二钝化层还接触第二电极，其一部分也通过开口暴露。 在另一个示例性实施例中，电流沿着集成电阻器（975，图9A）沿着薄膜层和钝化层之间的界面流动。

公开(公告)号：WO2007037976A2

公开(公告)日：2007-04-05

申请号：PCT/US2006/035452

申请日：2006-09-12

Applicant: AGILE MATERIALS AND TECHNOLOGIES, INC. ,  CHEN, Lee-yin, V.

Inventor： CHEN, Lee-yin, V.

IPC: H01L21/84 ,  H01L21/00 ,  H01L31/113 ,  H01L31/062

CPC classification number: H01L28/57 ,  H01L28/65

Abstract: Ferroelectric thin film devices including a passivation structure to reduce or control a leakage path between two electrodes and along an interface between a ferroelectric thin film layer and a passivation layer are described. Methods for fabricating such devices are also disclosed. The passivation structure includes a first passivation layer that includes an opening exposing a portion of the ferroelectric thin film layer allowing a second passivation layer to contact the thin film layer through the opening. In an exemplary embodiment, the opening is a rectangular ring surrounding an active region of a capacitor. In another exemplary embodiment, the second passivation layer also contacts the second electrode, a portion of which is also exposed through the opening. In another exemplary embodiment, current flows along the interface between the thin film layer and the passivation layer in an integrated resistor.

Abstract translation: 描述了包括钝化结构以减少或控制两个电极之间以及沿着铁电薄膜层和钝化层之间的界面的泄漏路径的铁电薄膜器件。 还公开了制造这种装置的方法。 钝化结构包括第一钝化层，该第一钝化层包括暴露铁电薄膜层的一部分的开口，允许第二钝化层通过该开口与薄膜层接触。 在示例性实施例中，开口是围绕电容器的有源区域的矩形环。 在另一示例性实施例中，第二钝化层还接触第二电极，其一部分也通过开口暴露。 在另一示例性实施例中，电流沿着集成电阻器中的薄膜层和钝化层之间的界面流动。

公开(公告)号：WO2006038974A2

公开(公告)日：2006-04-13

申请号：PCT/US2005/028321

申请日：2005-08-10

Applicant: TOKYO ELECTRON LIMITED ,  KO, Akiteru ,  XIA, Annie ,  CHEN, Lee

Inventor： KO, Akiteru ,  XIA, Annie ,  CHEN, Lee

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L21/0234 ,  H01J37/32706 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31645 ,  H01L29/517

Abstract: A method for plasma processing a high-k layer includes providing a substrate having a high-k layer formed thereon, on a substrate holder in a process chamber, and creating a plasma in the process chamber to thereby expose the high-k layer to the plasma. RF power is applied to the substrate holder, the RF power having a characteristic to reduce a rate of formation of an oxide interface layer located between the substrate and the high-k layer. A device includes a feature etched in a high-k layer. The etch profile of the device can include a reduced bird's beak, and a surface of the substrate in an etched region can be substantially coplanar with a substrate under a non-etched area.

Abstract translation: 用于等离子体处理高k层的方法包括在处理室中的衬底保持器上提供其上形成有高k层的衬底，并在处理室中产生等离子体，从而将高k层暴露于 等离子体。 RF功率施加到衬底保持器，RF功率具有降低位于衬底和高k层之间的氧化物界面层的形成速率的特性。 一种器件包括蚀刻在高k层中的特征。 器件的蚀刻轮廓可以包括缩小的鸟嘴，并且蚀刻区域中的衬底的表面可以在非蚀刻区域下与衬底基本共面。

公开(公告)号：WO2005071724A1

公开(公告)日：2005-08-04

申请号：PCT/US2004/041158

申请日：2004-12-09

Applicant: TOKYO ELECTRON LIMITED ,  CHEN, Lee ,  YUE, Hongyu ,  KAMBARA, Hiromitsu

Inventor： CHEN, Lee ,  YUE, Hongyu ,  KAMBARA, Hiromitsu

IPC: H01L21/3213

CPC classification number: H01L21/32134 ,  H01L21/28123 ,  H01L21/32136 ,  H01L21/32137

Abstract: A method and processing tool are provided for trimming a gate electrode structure containing a gate electrode layer with a first dimension. A reaction layer is formed through reaction with the gate electrode structure. The reaction layer is then selectively removed from the unreacted portion of the gate electrode structure by chemical etching, thereby forming a forming a trimmed gate electrode structure with a second dimension that is smaller than the first dimension. The trimming process can be carried out under process conditions where formation of the reaction layer is substantially self-limiting. The trimming process can be repeated to further reduce the dimension of the gate electrode structure.

Abstract translation: 提供了一种用于修整含有第一尺寸的栅电极层的栅电极结构的方法和处理工具。 通过与栅电极结构反应形成反应层。 然后通过化学蚀刻从栅电极结构的未反应部分选择性地除去反应层，从而形成具有小于第一尺寸的第二尺寸的修整的栅电极结构。 修整过程可以在反应层的形成基本上是自限制的工艺条件下进行。 可以重复修整过程以进一步减小栅电极结构的尺寸。

公开(公告)号：WO2003098662A2

公开(公告)日：2003-11-27

申请号：PCT/US2003/010469

申请日：2003-04-14

Applicant: TOKYO ELECTRON LIMITED ,  LUDVIKSSON, Audunn ,  CHEN, Lee

Inventor： LUDVIKSSON, Audunn ,  CHEN, Lee

IPC: H01L

CPC classification number: H01J37/32082 ,  H01L21/32136

Abstract: A method and apparatus are provided for plasma etching of Cu-containing layers in semiconductor devices using an aluminum source in the presence of a halogen-containing plasma. The aluminum source reacts with halogenated Cu-containing surfaces and forms volatile etch products that allows for anisotropic etching of Cu-containing layers using conventional plasma etching tools.

Abstract translation: 提供一种方法和装置，用于在含卤素等离子体存在下，使用铝源在半导体器件中等离子体蚀刻含Cu层。 铝源与卤化的含Cu表面反应并形成挥发性蚀刻产物，其允许使用常规等离子体蚀刻工具对含Cu层进行各向异性蚀刻。

公开(公告)号：WO2013049700A1

公开(公告)日：2013-04-04

申请号：PCT/US2012/058094

申请日：2012-09-28

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC. ,  ZHAO, Jianping ,  CHEN, Lee ,  FUNK, Merritt ,  IWAO, Toshihiko ,  VENTZEK, Peter

Inventor： ZHAO, Jianping ,  CHEN, Lee ,  FUNK, Merritt ,  IWAO, Toshihiko ,  VENTZEK, Peter

IPC: H01J37/32

CPC classification number: H01J37/32256 ,  H01J37/32247 ,  H01J37/32935 ,  H01L22/00

Abstract: The invention provides a plurality of resonator subsystems. The resonator subsystems can comprise one or more resonant cavities configured to couple electromagnetic (EM) energy in a desired EM wave mode to plasma by generating resonant microwave energy in a resonant cavity adjacent the plasma. The resonator subsystem can be coupled to a process chamber using one or more interface subsystems and can comprise one or more resonant cavities, and each resonant cavity can have a plurality of plasma tuning rods coupled thereto. Some of the plasma tuning rods can be configured to couple the EM-energy from one or more of the resonant cavities to the process space within the process chamber.

Abstract translation: 本发明提供了多个谐振器子系统。 谐振器子系统可以包括一个或多个谐振腔，其被配置为通过在与等离子体相邻的谐振腔中产生谐振微波能量将所期望的EM波模式中的电磁（EM）能量耦合到等离子体。 谐振器子系统可以使用一个或多个接口子系统耦合到处理室，并且可以包括一个或多个谐振腔，并且每个谐振腔可以具有耦合到其上的多个等离子体调谐棒。 一些等离子体调谐杆可被配置成将EM能量从一个或多个谐振腔耦合到处理室内的处理空间。

公开(公告)号：WO2012050747A2

公开(公告)日：2012-04-19

申请号：PCT/US2011/052225

申请日：2011-09-19

Applicant: A10 NETWORKS INC. ,  KANNAN, Lalgudi Narayanan ,  SZETO, Ronald Wai Lun ,  CHEN, Lee ,  XU, Feilong ,  JALAN, Rajkumar

Inventor： KANNAN, Lalgudi Narayanan ,  SZETO, Ronald Wai Lun ,  CHEN, Lee ,  XU, Feilong ,  JALAN, Rajkumar

IPC: H04L12/24 ,  H04L29/06 ,  G06F15/16

CPC classification number: H04L67/1008 ,  H04L67/02 ,  H04L67/1002

Abstract: A method, system, and computer program product for balancing servers based on server load status, include: receiving from a server a service response to a service request, the service response including a result from a processing of the service request and a server status indicating a computing load status of the server; obtaining the server status from the service response; receiving a next service request from a host, the next service request comprising a Uniform Resource Locator (URL); determining that the server is configured to process the URL; determining whether the server status indicates that the server is available to process the next service request; and in response to determining that the server status indicates that the server is available to process the next service request, sending the next service request to the server.

Abstract translation: 一种用于基于服务器负载状态平衡服务器的方法，系统和计算机程序产品，包括：从服务器接收对服务请求的服务响应，所述服务响应包括来自服务请求的处理的结果和指示 服务器的计算负载状态; 从服务响应获取服务器状态; 从主机接收下一服务请求，所述下一服务请求包括统一资源定位符（URL）; 确定服务器被配置为处理URL; 确定服务器状态是否指示服务器可用于处理下一个服务请求; 并且响应于确定服务器状态指示服务器可用于处理下一服务请求，将下一服务请求发送到服务器。