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91.发明公开Volt level shift method and corresponding circuit 失效Spannungspegelverschiebungsverfahren und entsprechende Schaltung
公开(公告)号：EP0725328A1
公开(公告)日：1996-08-07
申请号：EP95830025.3
申请日：1995-01-31
Inventor： Giacalone, Biagio , Bruno, Dario , Matranga, Vincenzo , Manaresi, Nicolò , Franchi, Eleonora
CPC classification number: H03F3/3001 , G05F3/242 , G05F3/262
Abstract: The present level shift circuit has a first (I1) and a second (I2) input respectively for input of a first and a second voltage signal and an output (OT) and comprises:
a) a first transistor (Q1) having a control terminal (G1), a first (S1) and a second (D1) main conduction terminal identifying a main conduction path, and
b) a second transistor (Q2) of the same type as said first transistor (Q1) and having a control terminal (G2), a first (S2) and a second (D2) main conduction terminal identifying a main conduction path.
The first signal is applied essentially between said control terminal (G1) and said first terminal (S1) of said first transistor (Q1) and said second input (I2) is coupled with the control terminal (G2) of said second transistor (Q2). The currents flowing in the conduction paths of the first (Q1) and the second (Q2) transistors are mutually proportional and one made from the other. The output (OT) is coupled with the first terminal (S2) of the second transistor (Q2). The control terminal (G1) of said first transistor (Q1) is connected to a potential reference (GND). The first signal is applied essentially to said first terminal (S1) of said first transistor (Q1).Abstract translation: 当前电平移位电路分别具有用于输入第一和第二电压信号和输出（OT）的第一（I1）和第二（I2）输入，并且包括：a）具有控制端子的第一晶体管（Q1） （G1），识别主导通路径的第一（S1）和第二（D1）主导电端子，以及b）与所述第一晶体管（Q1）相同类型的第二晶体管（Q2），并具有控制端子 G2），识别主导电路径的第一（S2）和第二（D2）主导电端子。 第一信号基本上在所述控制端（G1）和所述第一晶体管（Q1）的所述第一端（S1）之间施加，而所述第二输入（I2）与所述第二晶体管（Q2）的控制端（G2）耦合， 。 在第一（Q1）和第二（Q2）晶体管的导通路径中流动的电流是相互成比例的，另一个是由另一个制成的。 输出（OT）与第二晶体管（Q2）的第一端子（S2）耦合。 所述第一晶体管（Q1）的控制端子（G1）连接到电位基准（GND）。 第一信号基本上应用于所述第一晶体管（Q1）的所述第一端子（S1）。
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92.发明公开
公开(公告)号：EP0709790A1
公开(公告)日：1996-05-01
申请号：EP94830517.2
申请日：1994-10-31
Inventor： Bruno,Dario , Giacalone,Biagio , Manaresi, Nicolò
Abstract: Analog processor (2) of antecedent parts of fuzzy logic inference rules and comprising a plurality of analog generators (3) of membership function (FA) each having an output (4) supplying a value corresponding to a degree of truth complemented to one (α') of logical assignments of the type (A is A') with the outputs (4) being connected together to form a common circuit node (7) and also connected to a current generator (9) and the processor (2) comprising also a voltage control device (5) inserted between a supply voltage pole (V D ) and a ground voltage reference (GND) and a one-way element (8) connected to the common circuit node (7) and the one-way element (8) having an output (10) producing an overall degree of truth (Ω) for the antecedent part of the fuzzy rule to be processed.
Abstract translation: 模糊逻辑推理规则的先前部分的模拟处理器（2），包括多个隶属函数（FA）的模拟发生器（3），每个模拟发生器（3）具有输出（4），该输出（4）提供对应于一个（α （A）的逻辑分配，其中输出端（4）被连接在一起以形成公共电路节点（7）并且还连接到电流发生器（9），并且处理器（2）还包括 插入在电源电压极（VD）和接地电压基准（GND）之间的电压控制装置（5）和连接到公共电路节点（7）和单向元件（8）的单向元件（8） ）具有对待处理的模糊规则的先行部分产生总体真实度（OMEGA）的输出（10）。
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公开(公告)号：EP0684726A1
公开(公告)日：1995-11-29
申请号：EP94830197.3
申请日：1994-04-27
Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO , SGS-THOMSON MICROELECTRONICS S.r.l.
Inventor： Mancuso, Massimo , Poluzzi, Rinaldo , Rizzotto, Gianguido
CPC classification number: H04N7/012 , H04N7/0132
Abstract: A television signal scanning conversion device of the type comprising at least one filtering block (3) having a plurality of digital inputs (Pi, X) which receive through an interface (2) components (X, Pi) of an interlaced television signal comprises also at least one calculation block (CALC1) connected to the signal inputs and operating with fuzzy logic. Said calculation block is capable of executing a switch between at least two different interpolation procedures, to wit interfield and intrafield.
Abstract translation: 一种包括至少一个具有通过接口（2）接收隔行电视信号的分量（X，Pi）的数字输入（Pi，X）的至少一个滤波块（3）的类型的电视信号扫描转换设备还包括 至少有一个计算模块（CALC1）连接到信号输入端并用模糊逻辑运行。 所述计算块能够在至少两个不同的插值过程之间执行切换，即在场间和场内。
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94.发明公开Circuit for computing membership functions values in a fuzzy logic controller 失效Fertylogik-Steuerwerk中的Schaltung zum Berechnen von Mirgliedsfunktionswerten。
公开(公告)号：EP0675430A1
公开(公告)日：1995-10-04
申请号：EP94830157.7
申请日：1994-03-31
Inventor： Abruzzese, Massimo , Giacalone, Biagio
IPC: G06F7/60
CPC classification number: G06N7/04 , Y10S706/90
Abstract: Circuit for calculation of values of membership functions (FA) in a controller (1) operating with fuzzy logic procedures and said membership functions (FA) being of triangular or trapezoid form and defined in a so-called discourse universe (U) discretized in a finite number of points (m) and said controller (1) comprising a central control unit (3) equipped with a memory section (5) for memorization of said membership functions (FA) and connected to a microprocessor (9) in turn connected to an interface (13) and in which the membership functions (FA) are memorized by means of a codification (FA i ) of the coordinate of the vertex and the slopes at the sides of the vertex. The circuit comprises a calculator (11) connected to the memory section (5), to the microprocessor (9), and to the interface (13), to reconstruct the value (α) of each membership functions (FA) at each point of the discourse universe (U).
Abstract translation: 用于计算在模糊逻辑过程中操作的控制器（1）中的隶属函数（FA）的值的电路，并且所述隶属函数（FA）是三角形或梯形的并且在所谓的话语宇宙（U）中定义， 有限数量的点（m）和所述控制器（1）包括配备有用于存储所述隶属函数（FA）并连接到微处理器（9）的存储器部分（5）的中央控制单元（3），所述微处理器又连接到 接口（13），其中通过顶点坐标和顶点侧面的斜率的编码（FAi）来存储隶属函数（FA）。 电路包括连接到存储器部分（5），微处理器（9）和接口（13）的计算器（11），以重建每个隶属度函数（FA）的值（α） 话语宇宙（U）。
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95.发明公开Method for producing a stream of ionic aluminum 失效Verfahren und Generator zur Erzeugung von Aluminiumionen。
公开(公告)号：EP0637052A1
公开(公告)日：1995-02-01
申请号：EP93830335.1
申请日：1993-07-29
Inventor： Medulla, Candido , Raspagliesi, Mario
Abstract: The invention relates to a method and a generator for producing an aluminum ion flow, specifically for aluminum ion implantation in the microelectronics industry. The method comprises the following steps:
supplying a stream of an ionization gas into the ionization chamber;
providing an amount of an aluminum-containing feed material inside the ionization chamber;
generating, within the ionization chamber, an electron flow by supplying an electrode with a large current;
bombarding the ionization gas stream with the electron flow to create a plasma;
causing the plasma to attack the feed material so as to become enriched with aluminum ions;
taking the plasma out of the ionization chamber;
removing from the plasma, by application of a magnetic field, those ions which have a significantly different equivalent weight from the equivalent weight of the aluminum ions;
all this having selected the ionization gas and feed material such that, in the plasma taken out of the ionization chamber, there will be aluminum ions present along with other ions, all having different equivalent weights from the equivalent weight of the aluminum ions.Abstract translation: 本发明涉及一种用于生产铝离子流的方法和发生器，专门用于微电子工业中的铝离子注入。 该方法包括以下步骤：将电离气流送入电离室; 在电离室内提供一定量的含铝原料; 在电离室内通过供给具有大电流的电极而产生电子流; 用电子流轰击电离气流以产生等离子体; 导致等离子体侵袭原料，以富集铝离子; 将等离子体从电离室中取出; 通过施加磁场从等离子体中除去具有与铝离子当量重量相当的当量重量的那些离子; 所有这些都选择了电离气体和进料，使得在从电离室中取出的等离子体中将存在铝离子与其它离子一起存在，全部具有与铝离子的当量重量不同的当量重量。
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Patent Agency Ranking96.发明公开Monolithic integrated bridge transistor circuit and corresponding manufacturing process 失效Monolithisch integrierteBrückenschaltungmit Transistoren und entsprechendes Herstellungsverfahren。
公开(公告)号：EP0587968A1
公开(公告)日：1994-03-23
申请号：EP92830506.9
申请日：1992-09-18
Inventor： Zambrano, Raffaele , Palara, Sergio
CPC classification number: H01L27/0617
Abstract: A monolithically integrated, transistor bridge circuit of a type suiting power applications, comprises at least one pair of IGBT transistors (M1,M2). These IGBT transistors are laterally conducting, having drain terminals (9,19) formed on the surface of the integrated circuit (1), and through such terminals, they are connected to another pair of transistors (T1,T2) of the bipolar type.
The invention also relates to an associated process for manufacturing said bridge circuit.Abstract translation: 一种适合功率应用的单片集成的晶体管桥式电路，包括至少一对IGBT晶体管（M1，M2）。 这些IGBT晶体管是侧向导通的，具有形成在集成电路（1）的表面上的漏极端子（9,19），并且通过这些端子，它们连接到双极型的另一对晶体管（T1，T2）。 本发明还涉及用于制造所述桥式电路的相关联的方法。
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97.发明公开Process for forming buried regions, having different doping concentration, in monolitic semiconductor devices 失效一种用于用不同浓度的在单片半导体器件掩埋的掺杂区域的制造工艺。
公开(公告)号：EP0584436A1
公开(公告)日：1994-03-02
申请号：EP92830455.9
申请日：1992-08-26
Inventor： Zambrano, Raffaele , Alberio, Francesco
IPC: H01L21/00 , H01L21/266 , H01L21/74
Abstract: The invention relates to a process for forming buried regions having different doping concentrations in monolithic semiconductor devices comprising at least one pair of electronic components which incorporate said regions. Such regions are formed simultaneously by a single phototechnique and implantation operation using partial masking or screening of the areas exposed to the implantation.
Abstract translation: 本发明涉及一种方法，用于形成具有单片半导体器件不同的掺杂浓度的包含至少一对相配合所述区域的电子元件的掩埋区。 搜索区域通过使用部分掩蔽或暴露于植入区域的筛选单个图片技术和植入手术同时形成。
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公开(公告)号：EP0735580B1
公开(公告)日：2004-11-17
申请号：EP95830125.1
申请日：1995-03-31
Inventor： Zambrano, Raffaele
IPC: H01L21/762 , H01L21/763
CPC classification number: H01L21/763 , H01L21/76232
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99.发明授权Method for parallel processing of fuzzy logic inference rules and corresponding circuit architecture 失效一种用于模糊逻辑推理规则并行处理和匹配电路结构的方法
公开(公告)号：EP0684550B1
公开(公告)日：2003-03-26
申请号：EP94830241.9
申请日：1994-05-23
Inventor： Matranga, Vincenzo , Giacalone, Biagio , Abruzzese, Massimo
IPC: G06N7/04
CPC classification number: G06N7/04
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100.发明授权
公开(公告)号：EP0797165B1
公开(公告)日：2002-11-27
申请号：EP96830137.4
申请日：1996-03-21
Applicant: STMicroelectronics S.r.l. , CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
Inventor： Manganaro, Gabriele , Lavorgna, Mario , Lo Presti, Matteo , Fortuna, Luigi
CPC classification number: G06G7/26 , G06N3/0635
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