公开(公告)号：US20240222473A1

公开(公告)日：2024-07-04

申请号：US18684175

申请日：2022-12-20

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Feng LIN ,  Chaoqi XU ,  Shuxian CHEN ,  Chunxu LI ,  Li LU ,  Siyang LIU ,  Weifeng SUN

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66734 ,  H01L21/2251 ,  H01L29/0619 ,  H01L29/41741 ,  H01L29/7813

Abstract: The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.

公开(公告)号：US11984813B2

公开(公告)日：2024-05-14

申请号：US17435789

申请日：2020-05-15

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shen Xu ,  Siyu Zhao ,  Congming Qi ,  Sen Zhang ,  Xiaoyu Shi ,  Weifeng Sun ,  Longxing Shi

IPC: H02M3/335 ,  H02M1/00 ,  H02M1/38

CPC classification number: H02M3/33592 ,  H02M1/0058 ,  H02M1/38

Abstract: A synchronous rectification control system and method for a quasi-resonant flyback converter are provided. The control system includes a switching transistor voltage sampling circuit configured to sample an output terminal voltage of the switching transistor to obtain a sampled voltage of the switching transistor; a sampling calculation module configured to obtain a dead-time based on the sampled voltage of the switching transistor and a preset relationship, the preset relationship being a correspondence between the duration of the sampled voltage of the switching transistor being below a first preset value and the dead-time during an on-time of a switching cycle of the switching transistor, the dead-time being a time from when the switching transistor is turned off to when the synchronous rectification transistor is turned on; and a control module configured to receive the dead-time and control switching of the synchronous rectification transistor based on the dead-time.

公开(公告)号：US20240079404A1

公开(公告)日：2024-03-07

申请号：US18262100

申请日：2022-01-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jun SUN

IPC: H01L27/02

CPC classification number: H01L27/0259

Abstract: The present application relates to an electrostatic protection structure and a preparation method therefor. The electrostatic protection structure comprises a substrate, a buried layer, a first deep well, a second deep well and a third deep well. A well region of the opposite conductivity type and a heavily doped region of the same conductivity type are provided in the first deep well, and well regions and heavily doped regions of the same conductivity type are respectively provided in the second deep well and the third deep well. The first deep well, a first well region and a second well region are floating; a first heavily doped region leads out electrostatic voltage; and a sixth heavily doped region is grounded.

公开(公告)号：US20230268111A1

公开(公告)日：2023-08-24

申请号：US18308399

申请日：2023-04-27

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Congying DONG

IPC: H01F17/00 ,  H01L23/522

CPC classification number: H01F17/0013 ,  H01L23/5227 ,  H01F2017/0086

Abstract: A stacked spiral inductor, comprising: a substrate, and multiple stacked insulating layers and inductive metal layers formed on the substrate by means of a semiconductor process. Each inductive metal layer comprises a conductive coil in a shape of a spiral and a through hole area used for connecting two adjacent inductive metal layers. The conductive coils of the inductive metal layers have a common coil center. In two adjacent inductive metal layers, the conductive coil of the lower inductive metal layer is retracted toward the coil center with respect to the conductive coil of the upper inductive metal layer.

公开(公告)号：US11532726B2

公开(公告)日：2022-12-20

申请号：US17121360

申请日：2020-12-14

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng Bian

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423

Abstract: A VDMOS device and a manufacturing method therefor. The method comprises: forming a groove in a semiconductor substrate, wherein the groove comprises a first groove area, a second groove area and a third groove area communicating with the first groove area and the second groove area, and the width of the first groove area is greater than the widths of the second groove area and the third groove area; forming an insulation layer on the semiconductor substrate; forming a first polycrystalline silicon layer on the insulation layer; removing some of the first polycrystalline silicon layer; the first polycrystalline silicon layer forming in the first groove being used as a first electrode of a deep gate; removing all the insulation layer located on the surface of the semiconductor substrate and some of the insulation layer located in the groove; forming a gate oxide layer on the semiconductor substrate; forming a second polycrystalline silicon layer on the gate oxide layer; removing some of the second polycrystalline silicon layer; and the second polycrystalline silicon layer forming in the groove being used as a second electrode of a shallow gate.

公开(公告)号：US20220367722A1

公开(公告)日：2022-11-17

申请号：US17767333

申请日：2020-08-26

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Wangran WU ,  Guangan YANG ,  Feng LIN ,  Guipeng SUN ,  Yaohui WANG ,  Weifeng SUN ,  Longxing SHI

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: An IGZO thin-film transistor and a method for manufacturing same. The method comprises: acquiring a substrate; forming an IGZO layer on the substrate by means of a solution process; doping V impurities on a surface of the IGZO layer by means of a spin doping process; forming a source electrode at one side of the IGZO layer, and forming a drain electrode at the other side thereof; forming a gate dielectric layer on the doped IGZO layer; and forming a gate electrode on the gate dielectric layer.

公开(公告)号：US20220367682A1

公开(公告)日：2022-11-17

申请号：US17765295

申请日：2020-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Nailong HE ,  Sen ZHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/04 ,  H01L21/762

Abstract: A semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a semiconductor substrate. A first drift region is formed in the semiconductor substrate. A gate structure is formed on the semiconductor substrate A part of the gate structure covers a part of the first drift region. A first trench is formed in the first drift region, and a drain region is formed in the semiconductor substrate at the bottom of the first trench.

公开(公告)号：US20220352369A1

公开(公告)日：2022-11-03

申请号：US17761510

申请日：2020-08-20

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO.,LTD.

Inventor： JING ZHU ,  GUICHUANG ZHU ,  NAILONG HE ,  SEN ZHANG ,  SHAOHONG LI ,  WEIFENG SUN ,  LONGXING SHI

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10

Abstract: A laterally double-diffused metal oxide semiconductor device is provided, including: a drift region (3) having a first conductivity type; a first body region (10) disposed on the drift region (3) and having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; a first conductivity type region (13) disposed in the first body region (10); a second body region (12) disposed in the first conductivity type region (13) and having the second conductivity type; a source region (11) disposed in the second body region (12) and having the first conductivity type; and a contact region (9) disposed in the first body region (10) and having the second conductivity type.

公开(公告)号：US11462628B2

公开(公告)日：2022-10-04

申请号：US16771168

申请日：2018-11-13

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Guipeng Sun

IPC: H01L31/062 ,  H01L29/76 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device, and a manufacturing method thereof. The method includes: providing a semiconductor substrate provided with a body region, a gate dielectric layer, and a field oxide layer, formed on the semiconductor substrate; forming a gate polycrystalline, the gate polycrystalline covering the gate dielectric layer and the field oxide layer and exposing at least one portion of the field oxide layer; forming a drift region in the semiconductor substrate by ion implantation using a drift region masking layer as a mask, removing the exposed portion of the field oxide layer by further using the drift region masking layer as the mask to form a first field oxide self-aligned with the gate polycrystalline; forming a source region in the body region, and forming a drain region in the drift region; forming a second field oxide on the semiconductor substrate; and forming a second field plate on the second field oxide.

公开(公告)号：US20220302104A1

公开(公告)日：2022-09-22

申请号：US17639076

申请日：2020-08-06

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Danye LIANG ,  Guangyang WANG

IPC: H01L27/02

Abstract: In one aspect, a bidirectional Electro-Static Discharge (ESD) protection device includes: a first well region, a second well region and a third well region formed in a semiconductor substrate; two or more first injection regions and two or more second injection regions formed in the first well region, and two or more fourth injection regions and two or more fifth injection regions formed in the second well region; and third injection regions formed at a junction of the first well region and the third well region and at a junction of the second well region and the third well region.