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    Adaptive dead time control for push-pull switching circuits
    92.
    发明专利
    Adaptive dead time control for push-pull switching circuits 审中-公开
    用于推拉开关电路的自适应死时间控制

    公开(公告)号：JP2006191677A

    公开(公告)日：2006-07-20

    申请号：JP2006073531

    申请日：2006-03-16

    Applicant: Cirrus Logic Inc ,  シラス ロジック、インコーポレイテッド

    Inventor： MELANSON JOHN LAURENCE

    IPC: H03K17/16 ,  H03F1/32 ,  H03F3/217 ,  H03K5/151 ,  H03K17/687 ,  H03K17/92 ,  H03K19/00 ,  H03K19/0185

    CPC classification number: H03F1/32 ,  H03F3/2171 ,  H03K5/1515 ,  H03K19/0013 ,  H03K19/018585

    Abstract: PROBLEM TO BE SOLVED: To provide an apparatus and method for suppressing to a minimum a dead time within a switch circuit without incurring an overlap of ON conduction in switches.
    SOLUTION: An apparatus of the present invention includes: overlap detection circuitry (310) for measuring (406) the dead time/overlap of switches (104, 105); and control circuitry (320) for setting (408) the dead time to the optimum level (407) (generally the minimum possible dead time without any overlap occurring). The dead time/overlap may be detected by measuring the current through switches (501), the current into a power supply (601), the voltage waveform (710, 711, 712) at the switch point, or an average voltage waveform (803) at the switch point. The dead time may be controlled by utilizing delay elements (902, 903) prior to drivers (302, 303), or by utilizing circuitry (302a/320b) to control the driver timing.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于在开关电路内抑制最小死区时间的装置和方法，而不会导致开关中的ON导通的重叠。 解决方案：本发明的装置包括：用于测量（406）开关（104,105）的死区时间/重叠的重叠检测电路（310）; 以及控制电路（320），用于将死区时间设置为（408）至最佳电平（407）（通常为最小可能的死区时间而不发生任何重叠）。 可以通过测量通过开关（501）的电流，进入电源（601）的电流，开关点处的电压波形（710,711,712）或平均电压波形（803）来检测死区时间/重叠 ）在切换点。 可以通过在驱动器（302,303）之前利用延迟元件（902,903）或利用电路（302a / 320b）来控制驱动器定时来控制死区时间。 版权所有（C）2006，JPO＆NCIPI

    ERROR CORRECTION AND PARALLEL CHECK FOR PRODUCT CODE
    96.
    发明专利
    ERROR CORRECTION AND PARALLEL CHECK FOR PRODUCT CODE 失效

    公开(公告)号：JPH1155129A

    公开(公告)日：1999-02-26

    申请号：JP11399098

    申请日：1998-04-23

    Applicant: CIRRUS LOGIC INC

    Inventor： ZOOK CHRISTOPHER P

    IPC: G11B20/18 ,  G06F11/00 ,  H03M13/00

    Abstract: PROBLEM TO BE SOLVED: To provide a method of a P/Q decoder for generating a CRC syndrome concurrently with the correction of a product code. SOLUTION: A P/Q encoder/decoder 2 has a buffer 26 for storing read/write data, a controller 28 for arbitrating its access, a primary ECC/syndrome generator 29, a (Reed-Solomon) error corrector 30, and a secondary ECC generator/ correction checker (CRC) 32. When data are completely processed by using the primary ECC, for a multilayer error detection/correction EDAC, the check syndrome generated by the secondary ECC immediately checks the validity of correction, so that an unwanted path is removed when the uncorrectable error is not found after P or Q path end. When a code word having no error is skipped during the repeated paths of multidimensional primary ECC, the check syndrome of the secondary ECC compensates skipped data bytes.

    16/17 ENDEC FOR DECODING 17-BIT CODE WORD INTO 16-BIT DATA WORD, AND METHOD FOR DECODING 17-BIT CODE WORD INTO 16-BIT DATA WORD
    97.
    发明专利
    16/17 ENDEC FOR DECODING 17-BIT CODE WORD INTO 16-BIT DATA WORD, AND METHOD FOR DECODING 17-BIT CODE WORD INTO 16-BIT DATA WORD 失效

    公开(公告)号：JPH10134520A

    公开(公告)日：1998-05-22

    申请号：JP20349997

    申请日：1997-07-29

    Applicant: CIRRUS LOGIC INC

    Inventor： ZOOK CHRISTOPHER P

    IPC: G11B20/14 ,  G11B20/10 ,  H03M5/14 ,  H03M7/14 ,  H03M13/23 ,  H04L1/00 ,  H04L25/49 ,  H03M13/12

    Abstract: PROBLEM TO BE SOLVED: To provide an encoder/decoder(ENDEC) whose execution is not complicated and which can prevent an error in a decoding output from being propagated. SOLUTION: An encoder uses an identical mapping circuit so as to code the high-order byte and the low-order byte of an input data word. Without using a 1/(1+D ) precoder or an NRZ modulator in conventional cases, a data symbol b(n) 8 uses an NRZI modulator 172 so as to be written directly into a magnetic disk 18. A bit '1' inside the data symbol toggles a write current to a negative value from a positive value (or inversely) by using the modulator 172, and a bit '0' does not change a write current. When it is received, first 8 bits are decoded independently of last 8 bits so as to prevent their erroneous propagation. That is to say, the first 8 bits in a code word are decoded into a high-order byte in the decoded data word, and the last 8 bits are decoded into a low-order byte in the same manner, and both are decoded independently of each other.

    SYSTEM, DEVICE AND METHOD FOR FILLING UP TRANSMISSION ENABLE BITS AS PORTION OF SIZE CHANGE BIT BLOCK TRANSFER PROCESS
    98.
    发明专利
    SYSTEM, DEVICE AND METHOD FOR FILLING UP TRANSMISSION ENABLE BITS AS PORTION OF SIZE CHANGE BIT BLOCK TRANSFER PROCESS 失效

    公开(公告)号：JPH1091142A

    公开(公告)日：1998-04-10

    申请号：JP17466097

    申请日：1997-06-30

    Applicant: CIRRUS LOGIC INC

    Inventor： DYE THOMAS ANTHONY

    IPC: H04N1/393 ,  G06T3/40 ,  G09G5/36 ,  G09G5/377 ,  G09G5/39 ,  H04N1/46 ,  H04N1/60

    Abstract: PROBLEM TO BE SOLVED: To suppress the use of a host processor to a minimum and to efficiently generate a sprite by conducting a size change bit block transfer and a transmissive bit block transfer one process. SOLUTION: A graphic system has a host processor 50 which is coupled to a system bus 25, a system memory 75 which is connected to the processor 50 through a memory bus 131, a graphic processor 100, a frame buffer 85 and a display device 60. The processor 100 generates the pixel value which has a size change engine that executes a size change and a transmission enable process for a source pixel array in a single process and a color comparison logic. Then, the source pixel array, in which the size change and the transmission enable process are conducted, is written into a destination array. Moreover, the condition of transmission enable bits depend on a comparison output signal.

    HARDWARE SUPPORTING YUV DATA FORMAT CONVERSION FOR MPEG DECODER BY SOFTWARE
    99.
    发明专利
    HARDWARE SUPPORTING YUV DATA FORMAT CONVERSION FOR MPEG DECODER BY SOFTWARE 失效

    公开(公告)号：JPH1084557A

    公开(公告)日：1998-03-31

    申请号：JP6875797

    申请日：1997-03-21

    Applicant: CIRRUS LOGIC INC

    Inventor： KEENE DAVID

    IPC: H04N11/04 ,  G06F3/14 ,  G06T9/00 ,  G09G5/02 ,  G09G5/393

    Abstract: PROBLEM TO BE SOLVED: To relax processing by a host CPU by allowing a display controller to process with, a heavy load among decoding processing for motion picture encoding group (MPEG) data. SOLUTION: A display controller 320 conducts a task requiring a heavy load as rearrangement of YUV data with a non-pixel sequential format into data with a pixel sequential format, and U and V data are copied from one line to an adjacent line so as to copy the U and V data through the arithmetic operation by an internal BITBLIT engine 513. In this case, Y data on the adjacent line are protected from overwrite with byte masking. At the end of BITBLIT arithmetic operation, a signal denoting that the frame buffer is filled by new data is generated from the display controller 320 and the display controller 320 selects a frame buffer newly written automatically and reads data from the frame buffer.

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