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    Integrated circuit comprising a non-volatile memory
    91.
    发明授权
    Integrated circuit comprising a non-volatile memory 有权

    公开(公告)号：US12148503B2

    公开(公告)日：2024-11-19

    申请号：US17932694

    申请日：2022-09-16

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Xavier Lecoq

    IPC: G11C7/06 ,  G11C7/04 ,  G11C7/10

    Abstract: In an embodiment an integrated circuit includes a non-volatile memory having a plurality of memory cells, wherein each memory cell is configured to store information, and wherein each memory cell is configured to provide a reading current having an intensity dependent on a value stored in the memory cell when the memory cell is selected for reading; and a sense amplifier including a first amplifier configured to amplify the reading current of each memory cell selected for reading, an oscillation generator configured to generate on basis of the amplified signal a signal having oscillations according to a frequency dependent on the intensity of the current of the amplified signal, a counter configured to count the oscillations of the signal generated by the oscillation generator over at least one given period of time and a digital processing circuit configured to determine a value represented by the amplified signal on basis of the value counted during the at least one given period of time using a lookup table between values countable by the counter and values representable by the amplified signal.

    ELECTRONIC CIRCUIT FOR IMAGE SENSING
    95.
    发明公开
    ELECTRONIC CIRCUIT FOR IMAGE SENSING 审中-公开

    公开(公告)号：US20240334080A1

    公开(公告)日：2024-10-03

    申请号：US18616454

    申请日：2024-03-26

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Laurent SIMONY

    IPC: H04N25/616 ,  H03F3/45 ,  H04N25/709 ,  H04N25/77

    CPC classification number: H04N25/616 ,  H03F3/45475 ,  H04N25/709 ,  H04N25/77 ,  H03F2200/69

    Abstract: An electronic circuit includes image acquisition cells, wherein each cell has a photodetector coupled to a first node of the cell, and an amplifying transistor having a gate connected to the first node, a conduction node coupled to an output of the cell, and a node for controlling a back gate voltage. The amplifying transistor is configured so that its threshold voltage varies according to the back gate voltage. A control circuit adjusts a voltage applied to the control node of the back gate voltage of the amplifying transistor of one of the cells according to a comparison of the voltage present at the cell output and a reference voltage.

    Reading circuit for a pixel array
    96.
    发明授权
    Reading circuit for a pixel array 有权

    公开(公告)号：US12081888B2

    公开(公告)日：2024-09-03

    申请号：US17660084

    申请日：2022-04-21

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Alexandre Mas ,  Abdessamed Mekki ,  Cedric Tubert

    IPC: H04N25/75 ,  H03M1/12 ,  H03M1/46 ,  H04N25/625 ,  H04N25/677

    CPC classification number: H04N25/75 ,  H03M1/1245 ,  H03M1/46 ,  H04N25/625 ,  H04N25/677

    Abstract: The present disclosure relates to a read-out circuit comprising N inputs configured to be connected to N respective outputs of a pixel array of an image sensor, with N being an integer strictly greater than 1; and N analog-to-digital converters organized in K groups, with K being an integer strictly greater than 1 and strictly less than N, and each having a first input coupled to a respective one of the N inputs and a second input. In each group, the second inputs of the analog-to-digital converters of the group are connected together, electrically decoupled from the second inputs of the analog-to-digital converters of the other groups, and configured to receive a first reference signal that is identical for all the analog-to-digital converters of the group.

    Inrush current of at least one low drop-out voltage regulator
    97.
    发明授权
    Inrush current of at least one low drop-out voltage regulator 有权

    公开(公告)号：US12072724B2

    公开(公告)日：2024-08-27

    申请号：US17453815

    申请日：2021-11-05

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Alexandre Pons

    IPC: G05F1/575

    CPC classification number: G05F1/575

    Abstract: The present disclosure relates to a device comprising: N low drop-out voltage regulators, N being an integer greater than or equal to 1; a first circuit configured to deliver N set-point voltages to the N regulators which are proportional to the same first current; and a second circuit configured to deliver the first current, wherein the first current is proportional to a reference current modulated based on a sum of the inrush currents of the N regulators.

    Voltage converter and method
    98.
    发明授权
    Voltage converter and method 有权

    公开(公告)号：US12057773B2

    公开(公告)日：2024-08-06

    申请号：US18359548

    申请日：2023-07-26

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： David Chesneau

    IPC: H02M3/158

    CPC classification number: H02M3/158

    Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator configured to compare a first voltage with a threshold, the first voltage being equal, during a first period, to a first increasing ramp and, during a second period, to a second decreasing ramp, the threshold having a first value during the first period and a second value during the second period, the first and second values being variable.

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