公开(公告)号：KR1020120057758A

公开(公告)日：2012-06-07

申请号：KR1020100119234

申请日：2010-11-27

Applicant: 서울대학교산학협력단

Inventor： 이종호 ,  장정원 ,  유상배 ,  김성준 ,  이태형

IPC: A61N1/372 ,  A61C8/00

Abstract: PURPOSE: An implant for neurotization by using electro stimulation is provided to increase bone density and early bone fusion. CONSTITUTION: An implant for neurotization by using electro stimulation comprises an insertion body, a stimulating electrode(200), an electrode tip(300) which is in contact with nerves located inside the alveolar bone, a power supply(400) which is installed in a space part(122), a printed circuit board(500), and a magnetic pole chip(600) which is electrically connected to upper end of the stimulating electrode. The insertion body comprises a body(110) which has a penetration hole(114) in center area and screw threads(112) in edges in order to be screwed inside an alveolar bone and a head. Lower part of the stimulating electrode is exposed to outside the body by being inserted into the penetration hole.

Abstract translation: 目的：提供用于通过电刺激进行神经降解的植入物，以增加骨密度和早期骨融合。 构成：通过使用电刺激进行神经化的植入物包括：插入体，刺激电极（200），与位于牙槽骨内部的神经接触的电极末端（300）;电源（400），安装在 空间部分（122），印刷电路板（500）和电极连接到刺激电极的上端的磁极片（600）。 插入体包括主体（110），其在中心区域具有穿透孔（114）并且边缘具有螺纹（112），以便被拧入牙槽骨和头部内部。 刺激电极的下部通过插入穿透孔而暴露于身体外部。

公开(公告)号：KR1020110119156A

公开(公告)日：2011-11-02

申请号：KR1020100038691

申请日：2010-04-26

Applicant: 서울대학교산학협력단

Inventor： 이종호

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/0688 ,  H01L27/11551

Abstract: PURPOSE: A three dimensional vertical memory cell string with a shield electrode, a memory array using the same, and a manufacturing method thereof are provided to improve integration by reducing the width of a trench between adjacent cell stacks. CONSTITUTION: Electrode stacks are formed by filling a selectively etched sacrificial semiconductor layer with an insulation layer. A gate insulation layer stack including a charge storage layer(3) is formed on each trench. A semiconductor body(5) is formed on the gate insulation layer stack. A separation insulation layer(6) is formed on each trench and surrounds the semiconductor body. A shield electrode(27) is formed on the separation insulation layer of each trench by depositing conductive materials on the semiconductor substrate and etching the semiconductor substrate.

Abstract translation: 目的：提供具有屏蔽电极的三维垂直存储单元串，使用其的存储器阵列及其制造方法，以通过减小相邻单元堆叠之间的沟槽的宽度来改善积分。 构成：通过用绝缘层填充选择性蚀刻的牺牲半导体层来形成电极堆叠。 在每个沟槽上形成包括电荷存储层（3）的栅极绝缘层堆叠。 半导体本体（5）形成在栅极绝缘层叠层上。 在每个沟槽上形成分隔绝缘层（6）并围绕半导体本体。 通过在半导体衬底上沉积导电材料并蚀刻半导体衬底，在每个沟槽的隔离层上形成屏蔽电极（27）。

公开(公告)号：KR1020100119625A

公开(公告)日：2010-11-10

申请号：KR1020090038652

申请日：2009-05-01

Applicant: 서울대학교산학협력단

Inventor： 이종호

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L21/28273 ,  H01L27/0688 ,  H01L27/2481 ,  H01L29/513

Abstract: PURPOSE: A high-density vertical-type semiconductor memory cell string, a cell string array and a fabricating method thereof are provided to increase the integration of the semiconductor by enabling cells to share a multi-layer control electrode stack. CONSTITUTION: A first insulating layer(6) is perpendicularly formed on a semiconductor substrate(1). A semiconductor body(5) is formed in both side of the first insulating layer. Gate stacks(2,3,4) are formed in both side of the semiconductor body. A control electrode(8) is formed with a multiple layer and is formed one side of the gate stacks.

Abstract translation: 目的：提供高密度垂直型半导体存储器单元串，单元串阵列及其制造方法，以通过使单元能够共享多层控制电极堆叠来增加半导体的集成。 构成：在半导体衬底（1）上垂直地形成第一绝缘层（6）。 半导体本体（5）形成在第一绝缘层的两侧。 栅叠层（2,3,4）形成在半导体本体的两侧。 控制电极（8）由多层形成并形成在栅叠层的一侧。

公开(公告)号：KR1020100102394A

公开(公告)日：2010-09-24

申请号：KR1020090020744

申请日：2009-03-11

Applicant: 서울대학교산학협력단

Inventor： 이종호

IPC: H01L27/115 ,  H01L21/8247 ,  B82Y10/00

CPC classification number: G11C16/0483 ,  G11C16/10 ,  H01L27/2463

Abstract: PURPOSE: A high integrated flash memory cell device, a cell string, and a manufacturing method thereof are provided to simplify a manufacturing process by removing a source and drain channel. CONSTITUTION: A first doping semiconductor region(1) is formed on a semiconductor substrate. A second doping semiconductor region(2) is doped with opposite impurities to the first doping semiconductor region and is formed on the first doping semiconductor region. A third doping semiconductor region(24) is made of materials with different band gap from the second doping semiconductor region and is formed on the second doping semiconductor region.

Abstract translation: 目的：提供高集成闪存单元装置，单元串及其制造方法，以通过去除源极和漏极通道来简化制造过程。 构成：在半导体衬底上形成第一掺杂半导体区域（1）。 第二掺杂半导体区域（2）掺杂有与第一掺杂半导体区域相反的杂质，并形成在第一掺杂半导体区域上。 第三掺杂半导体区域（24）由与第二掺杂半导体区域具有不同带隙的材料制成并形成在第二掺杂半导体区域上。