Abstract:
A method of preventing successive packet errors according to a full receiver buffer in a selective repeat hybrid ARQ(Automatic Repeat Request) system is provided to efficiently use a bandwidth in case of coupling and using a hybrid ARQ and a selective ARQ in a system with a long round trip delay time. A method of preventing successive packet errors according to a full receiver buffer in a selective repeat hybrid ARQ(Automatic Repeat Request) system includes the steps of: transmitting a data packet to a receiver from a central station(401); checking the storage information of the data packet in an NACK(Negative ACKnowledgement) packet(404); storing the data packet in a re-transmission queue after transmitting a packet of parity bits to the receiver in case that the data packet is stored in the buffer(405,406); and maintaining the data packet stored in a transmission queue after re-transmitting the data packet in case that the data packet is not stored in the buffer(407,408).
Abstract:
1. 청구범위에 기재된 발명이 속한 기술분야 본 발명은 OFDM 시스템에서 PN 수열을 이용한 프리엠블 수열 생성 방법과, 시간 동기 및 주파수옵셋 추정 방법에 관한 것임. 2. 발명이 해결하려고 하는 기술적 과제 본 발명은, OFDM 시스템의 송신측에서는 시간 도메인에서 자기상관 성질이 좋은 PN 수열이 되도록 주파수 도메인상에서 프리엠블 신호를 생성하고, 수신측에서는 상기 프리엠블 수열 생성시 사용된 PN(Pseudo Noise)수열을 이용하여 시간 도메인에서 심볼 동기 및 부반송파 주파수 옵셋 추정을 수행함으로써, OFDM 시스템에서 PN 수열을 이용한 프리엠블 수열 생성 방법과, 시간 동기 및 주파수옵셋 추정 방법을 제공하는데 그 목적이 있음. 3. 발명의 해결방법의 요지 본 발명은, OFDM 수신 시스템에서의 시간동기 및 주파수 옵셋 추정 방법에 있어서, 시간 도메인상에서 OFDM 수신신호의 프리엠블의 위치를 찾아 심볼 동기를 맞추는 시간동기 단계; 및 상기 시간동기 단계에서 동기화된 수신신호에 상기 PN 수열을 차동 부호화한 수열을 곱함으로써, 시간도메인 상에서 부반송파의 주파수 옵셋을 추정하는 주파수옵셋 추정 단계를 포함함. 4. 발명의 중요한 용도 본 발명은 OFDM 시스템에서의 시간 동기 및 주파수옵셋 추정 등에 이용됨. 직교 주파수 분할 다중화, OFDM, 프리엠블 수열, PN 수열, 주파수 옵셋 추정, 시간 동기
Abstract:
A soft decision demodulation apparatus and a method thereof are provided to obtain a highly efficient bandwidth and a high performance by decoding repeatedly based on a soft decision value. A storing unit predetermines and stores the nearest constellation point of an opposite bit corresponding to a point of each constellation by dividing a constellation point region. A quantization unit(201) quantizes a channel receiving signal. A region determination unit(202) determines the nearest constellation point corresponding to the channel receiving signal quantized by the quantizing unit(201). An opposite constellation point detection unit(204) detects the nearest constellation point of the opposite bit corresponding to the nearest constellation point determined by the quantization unit(201) from the value previously stored in the storing unit. A soft decision demodulation value calculation unit(203) calculates a soft decision demodulation value based on the nearest constellation point determined by the region determination unit(202), the nearest constellation point of the opposite bit detected from the opposite constellation point detection unit(204), and the channel receiving unit.
Abstract:
A method for optimizing phase factors in partial transmit sequence orthogonal frequency division multiplexing system. The method includes initializing sub-block signals by applying an initial phase factor to the sub-block signals in all sub-blocks; setting a reference peak value with a peak value of a signal formed by combining the sub-block signals; selecting a phase value that minimizes the peak value of an output signal as the phase factor of each sub-block by applying a next phase value to each sub-block signal as the phase factor, and repeating this with respect to the remaining available phase values.
Abstract:
PURPOSE: A scrambling system and method in a multi-carrier CDMA and a recording medium storing its program are provided to reduce a PARR(Peak-to-Average Power Ratio) by changing a scrambling code according to user's combination of orthogonal codes. CONSTITUTION: A symbol modulator modulates a bit sequence of the kth user into symbols(S1), and a multiplier multiplies each modulated symbols to an orthogonal code to spread it to a chip sequence(S2). An adder adds the spread chip sequences in synchronization with a symbol timing, and an interleaver performs interleaving on chip sequences of M number of symbols to be transmitted and aligns chips making the same symbols at M-chip intervals(S3). A serial/parallel converter converts the aligned chip sequences into a parallel chip signal having the number of sub-carriers(S4), and a scrambling chip vector generator and a multiplier multiply the parallel chip signal to a scrambling code and transmit it to an inverse Fourier converter(S5). The inverse Fourier converter, the parallel/serial converter and a guard time inserting unit modulate one chip of each sub-carrier to generate a multi-carrier signal, and output it(S6).