公开(公告)号：KR100836625B1

公开(公告)日：2008-06-10

申请号：KR1020060124500

申请日：2006-12-08

Applicant: 한국전자통신연구원

Inventor： 정희상 ,  최영민 ,  좌혜경 ,  박형준

IPC: G06F17/14

CPC classification number: G06F17/141

Abstract: A DFT(double Fourier Transform) device and a method thereof are provided to realize a DFT operation through hardware in a field needing DFT for data not a multiplier of two, reduce a memory by reading data from a buffer and storing the data to the buffer, and reduce latency and increase throughout by reducing an interval between input and output for the DFT. A buffer(200) stores data and a single stage unit(300) generates FT data by performing the FT for the data stored in the buffer. An entire stage controller(100) enables the buffer to store the data, forms a plurality of single stages respectively corresponding to a plurality of even numbers factorizing a resource unit of the data, and controls the FT by using the single stage unit for a plurality of single stage. The entire stage controller is equipped with an even number former(101) including entire stage structure information including the number and the order of single stages corresponding to a plurality of even numbers, and the even number of each single stage, and controls the single stage according to the entire stage structure information for the data stored in the even number former.

Abstract translation: 提供了DFT（双傅立叶变换）装置及其方法，以便在需要DFT的场中通过硬件实现DFT操作，而不是二进制数的数据，通过从缓冲器读取数据并将数据存储到缓冲器来减少存储器 ，并通过减少DFT的输入和输出间隔来减少延迟并增加。 缓冲器（200）存储数据，单级单元（300）通过对存储在缓冲器中的数据执行FT来生成FT数据。 整个级控制器（100）使得缓冲器能够存储数据，形成分别对应于分解数据的资源单元的多个偶数的多个单级，并且通过使用单级单元来控制FT 的单阶段。 整个舞台控制器配备有偶数编号（101），包括整个舞台结构信息，包括与多个偶数相对应的单级的数量和顺序，以及每个单级的偶数，并且控制单级 根据存储在偶数编号中的数据的整个阶段结构信息。

公开(公告)号：KR1020080039790A

公开(公告)日：2008-05-07

申请号：KR1020070102543

申请日：2007-10-11

Applicant: 한국전자통신연구원 ,  삼성전자주식회사

Inventor： 김태중 ,  박기윤 ,  김남일 ,  이재경 ,  박형준 ,  방승찬

IPC: H04L1/00 ,  H04B1/02 ,  H04B1/04 ,  H04L29/02

CPC classification number: H04L1/0002 ,  H04L1/0033 ,  H04L1/0041 ,  H04L1/0061 ,  H04L1/0067 ,  H04L1/0071

Abstract: A transmission method for a data rate matching and an apparatus thereof are provided to prevent a punch for data having a high weight value by performing efficient data rate matching based on a variably allocated resource. A transmission method for a data rate matching includes the steps of: receiving a coded input signal based on a predetermined coding rate(S100), and segmenting the received input signal into a systematic bit and a plurality of parity bits based on the coding rate(S110); matching the parity bits based on a size of a received buffer(S120); performing a data rate matching for the parity bits and the systematic bit based on resource information for a physical channel allocated on an input signal and information for a resource which is additionally punched (S130,S140); and integrating the systematic bit and the parity bits which are matched in the second matching step(S150).

Abstract translation: 提供一种用于数据速率匹配的传输方法及其装置，以通过基于可变分配的资源执行有效的数据速率匹配来防止具有高权重值的数据的打孔。 一种用于数据速率匹配的传输方法包括以下步骤：基于预定的编码率接收编码的输入信号（S100），并且基于编码率将接收的输入信号分割为系统位和多个奇偶校验位（ S110）; 基于接收到的缓冲器的大小来匹配奇偶校验位（S120）; 基于对输入信号分配的物理信道的资源信息和附加穿孔的资源的信息，执行奇偶校验位和系统位的数据速率匹配（S130，S140）。 以及对在第二匹配步骤中匹配的系统位和奇偶校验位进行积分（S150）。

公开(公告)号：KR100823569B1

公开(公告)日：2008-04-21

申请号：KR1020060116951

申请日：2006-11-24

Applicant: 한국전자통신연구원

Inventor： 정민호 ,  박형준 ,  이용환

IPC: H04B1/10 ,  H03M13/09 ,  H04L27/26

Abstract: 본 발명은 부분적으로 대역이 중첩되는 단일 반송파 간섭 신호의 제거 방법 및 장치에 관한 것이다.
이를 위하여 본 발명은 입력 신호를 기저 대역으로 하향 천이시키는 전 처리 모듈, 입력 신호를 인터폴레이션 비율로 나누어, 간섭 신호를 제거하는 간섭 신호 제거 모듈, 간섭 신호 제거 모듈의 출력을 통과 대역 신호로 변환하는 후 처리 모듈 및 잔여 간섭 신호의 데시메이션을 실행한 뒤 간섭 신호 제거 모듈로 피드백시키는 오류 피드백 프로세서 모듈을 포함하는 간섭 신호 제거 장치를 제공한다. 또한, 간섭 신호가 포함된 입력 신호를 기저 대역으로 하향 천이시켜서 인터폴레이션 및 필터링을 수행한 뒤, 원래 신호의 주파수로 천이시켜 발생된 잔여 간섭 신호를 데시메이션하는 간섭 신호 제거 방법을 제공한다.
본 발명에 의하면, 인터폴레이션 필터 및 데시메이션 필터를 사용함으로써, 간섭 신호 제거 장치의 구현의 복잡도가 감소하며, 간섭 신호 제거를 느린 속도로 처리할 수 있어, 계산의 복잡도가 매우 감소하는 효과를 기대할 수 있다.
단일 반송파 간섭 신호, 간섭 신호 제거, 인터폴레이션, Interpolation, 데시메이션, Decimation, XC, 필터형-X 알고리즘

公开(公告)号：KR100776647B1

公开(公告)日：2007-11-19

申请号：KR1020060095816

申请日：2006-09-29

Applicant: 한국전자통신연구원

Inventor： 황현구 ,  박형준

IPC: H04J11/00 ,  H04B1/7085

CPC classification number: H04L27/266 ,  H04B1/7085 ,  H04L25/0224 ,  H04L27/2675 ,  H04L27/2695

Abstract: An apparatus and a method for estimating a frequency offset are provided to prevent the performance of estimating the frequency offset from being deteriorated due to multipath and to reduce power consumption in the other area except a cell boundary. A cross-correlation unit(301) correlates first and second parts of a reception reference signal with a reference signal previously stored to output first and second cross-correlation signals. A first sample accumulator accumulates the first cross-correlation signals output from the cross-correlation section by N/2 numbers. A second sample accumulator accumulates the second cross-correlation signals output from the cross-correlation section by N/2 numbers. A phase calculator(303) calculates a phase of a frequency offset by using signals output from the first and the second sample accumulators. A frequency offset estimator(306) estimates a frequency offset using complex number output from the phase calculator.

Abstract translation: 提供了一种用于估计频率偏移的装置和方法，以防止频率偏移的估计性能由于多路径而劣化，并且降低除了单元边界之外的其它区域的功率消耗。 互相关单元（301）将接收参考信号的第一和第二部分与预先存储的参考信号相关联，以输出第一和第二互相关信号。 第一采样累加器将从互相关部分输出的第一互相关信号累加N / 2个数。 第二采样累加器累积从互相关部分输出的第二互相关信号N / 2个数。 相位计算器（303）通过使用从第一和第二样本累加器输出的信号来计算频率偏移的相位。 频率偏移估计器（306）使用来自相位计算器的复数输出来估计频率偏移。

公开(公告)号：KR1020070061747A

公开(公告)日：2007-06-14

申请号：KR1020060116965

申请日：2006-11-24

Applicant: 한국전자통신연구원

Inventor： 정민호 ,  박형준

IPC: H04L27/26 ,  H04B7/04 ,  H04B7/06 ,  H04B7/155

CPC classification number: H04L27/2628

Abstract: An apparatus for modulating a multi antenna for downlink OFDMA wireless communication and a method for implementing the same are provided to implement a base station modulation apparatus of an OFDMA system which transmits downlink data by using a multi antenna and a multi subcarrier at the same time. An apparatus for modulating a multi antenna for downlink OFDMA wireless communication includes a DTP(Downlink Traffic Packet) processing unit(510), an index mapper(520), a scrambler(530), a virtual carrier insertion unit(540), an IFFT(Inverse Fast Fourier Transform) unit(550), and a CP(Cyclic Prefix) insertion unit(570). The DTP processing unit(510) generates a DTP symbol value by mapping downlink data to an antenna of a plurality of antennas to be transmitted. The index mapper(520) maps the DTP symbol value received from the DTP processor(510) to the number of bits for transmission. The scrambler(530) performs a scrambling operation which randomizes interference between cells of the downlink data transmitted through the index mapper(520). The virtual carrier insertion unit(540) fills virtual data in an empty space of the scrambled downlink data. The IFFT unit(550) performs an inverse fast fourier transform operation which transforms the data transmitted from the virtual carrier insertion unit(540) to a signal of a time axis. The CP insertion unit(570) adds a CP to the inverse fast Fourier transformed downlink data.

Abstract translation: 提供一种用于下行OFDMA无线通信的多天线调制装置及其实现方法，以实现OFDMA系统的基站调制装置，其通过同时使用多天线和多子载波来发送下行链路数据。 用于下行OFDMA无线通信的多天线调制装置包括DTP（下行链路业务分组）处理单元（510），索引映射器（520），加扰器（530），虚拟载波插入单元（540），IFFT （快速傅里叶逆变换）单元（550）和CP（循环前缀）插入单元（570）。 DTP处理单元（510）通过将下行链路数据映射到要发送的多个天线的天线来生成DTP符号值。 索引映射器（520）将从DTP处理器（510）接收的DTP符号值映射到用于传输的位数。 加扰器（530）执行随机化通过索引映射器（520）发送的下行链路数据的小区之间的干扰的加扰操作。 虚拟载波插入单元（540）在加扰的下行链路数据的空白空间填充虚拟数据。 IFFT单元（550）执行将从虚拟载波插入单元（540）发送的数据变换为时间轴的信号的逆快速傅里叶变换操作。 CP插入单元（570）将CP添加到快速傅里叶逆变换的下行链路数据。

公开(公告)号：KR1020070061745A

公开(公告)日：2007-06-14

申请号：KR1020060116951

申请日：2006-11-24

Applicant: 한국전자통신연구원

Inventor： 정민호 ,  박형준 ,  이용환

IPC: H04B1/10 ,  H03M13/09 ,  H04L27/26

CPC classification number: H04B1/1036 ,  H04L25/03006 ,  H04L27/2691

Abstract: An apparatus for canceling crosstalk due to the partial overlap of a frequency band and its method are provided to reduce the complexity of calculation required for canceling crosstalk by removing the necessity of using a high sampling frequency. A pre-processor module(210) downwardly transfers an input signal including crosstalk to a baseband. A crosstalk canceling module(220) divides the downwardly-transferred input signal by an interpolation rate, and cancels the crosstalk of the input signal. A post-processing module(230) converts an output of the crosstalk canceling module(220) into a pass band signal. An error feedback processor module(240) receives a remnant crosstalk from the post-processing module(230), executes decimation, and feeds it back to the crosstalk canceling module(220).

Abstract translation: 提供了用于消除由于频带的部分重叠引起的串扰的装置及其方法，以通过消除使用高采样频率的必要性来减少消除串扰所需的计算的复杂度。 预处理器模块（210）将包括串扰的输入信号向下传送到基带。 串扰消除模块（220）将向下传输的输入信号除以内插速率，并消除输入信号的串扰。 后处理模块（230）将串扰消除模块（220）的输出转换成通带信号。 错误反馈处理器模块（240）从后处理模块（230）接收剩余的串扰，执行抽取，并将其馈送回到串扰消除模块（220）。

公开(公告)号：KR1020070061128A

公开(公告)日：2007-06-13

申请号：KR1020060049731

申请日：2006-06-02

Applicant: 한국전자통신연구원

Inventor： 윤병호 ,  박형준

IPC: H04L29/02 ,  H04L12/28

CPC classification number: H04W88/18 ,  H04L29/10 ,  H04L41/24

Abstract: A data processing apparatus and a method having a data flow channel in a wireless communication system are provided to improve data processing speed and support expanded data processing capacity by processing the high capacity of data through high speed hardware. A data processing apparatus having a data flow channel in a wireless communication system includes a main processor unit(300), a data storing unit(400), a MAC(Media Access Control) unit(500), a modem unit(600), and a modem controlling unit. The main processor unit(300) receives data, divides the data into processable capacity in the wireless communication system, and outputs the data. The data storing unit(400) stores the data output from the main processor unit(300), and outputs the stored data. The MAC unit(500) processes the data output from the data storing unit(400), and outputs the data. The modem unit(600) processes and outputs the data output from the MAC unit(500) through one process among encoding, decoding, modulating, and demodulating processes. The modem controlling unit generates a control signal controlling the main processor unit, the MAC unit, and the modem unit, and outputs the signal.

Abstract translation: 提供了一种在无线通信系统中具有数据流通道的数据处理装置和方法，以通过高速硬件处理高容量数据来提高数据处理速度并支持扩展的数据处理能力。 在无线通信系统中具有数据流通道的数据处理装置包括主处理器单元（300），数据存储单元（400），MAC（媒体访问控制）单元（500），调制解调器单元（600） 和调制解调器控制单元。 主处理器单元（300）接收数据，将数据划分为无线通信系统中的可处理容量，并输出数据。 数据存储单元（400）存储从主处理器单元（300）输出的数据，并输出存储的数据。 MAC单元（500）处理从数据存储单元（400）输出的数据，并输出数据。 调制解调器单元（600）通过编码，解码，调制和解调处理中的一个处理来处理和输出从MAC单元（500）输出的数据。 调制解调器控制单元产生控制主处理器单元，MAC单元和调制解调器单元的控制信号，并输出该信号。

公开(公告)号：KR1020070061127A

公开(公告)日：2007-06-13

申请号：KR1020060049730

申请日：2006-06-02

Applicant: 한국전자통신연구원

Inventor： 윤병호 ,  박형준

IPC: H04L1/08 ,  H04L1/20

CPC classification number: H04L1/20 ,  H04L1/004 ,  H04L1/08

Abstract: An apparatus and a method for testing signal integrity at a wireless communication system with a modem function are provided to test integrity of all signals of hardware for processing modem data with high speed and large capacity. An apparatus for testing signal integrity at a wireless communication system with a modem function includes a random number data/CRC(Cyclic Redundancy Code) generating unit(100), a data comparing unit(300,310,320), and a data storing unit(200,210). The random number data/CRC generating unit(100) generates random number data based on inputted data, and generates and outputs a CRC of the generated random data. The data comparing unit(300,310,320) parallel receives the random number data and the CRC outputted from the random number data/CRC generating unit(100), generates the CRC from the random number data, compares the generated CRC and the inputted CRC, and tests integrity of the inputted data. The data storing unit(200,210) consists of a storing unit storing the random number data and a CRC storing unit storing the CRC, and parallel stores the random number data outputted from the random number data/CRC generating unit(100) and the data comparing unit(300,310,320), and the CRC generated from the random number data/CRC generating unit(100) and the data comparing unit(300,310,320).

Abstract translation: 提供了一种用于在具有调制解调器功能的无线通信系统上测试信号完整性的装置和方法，以测试用于处理具有高速和大容量的调制解调器数据的硬件的所有信号的完整性。 用于在具有调制解调器功能的无线通信系统中测试信号完整性的装置包括随机数数据/ CRC（循环冗余码）生成单元（100），数据比较单元（300,310,320）和数据存储单元（200,210）。 随机数数据/ CRC生成部（100）根据输入的数据生成随机数数据，生成并输出所生成的随机数据的CRC。 数据比较单元（300,310,320）并行接收随机数数据和从随机数数据/ CRC生成单元（100）输出的CRC，从随机数数据生成CRC，比较生成的CRC和输入的CRC，并进行测试 输入数据的完整性。 数据存储单元（200,210）包括存储随机数数据的存储单元和存储CRC的CRC存储单元，并且并行地存储从随机数数据/ CRC生成单元（100）输出的随机数数据和数据比较 单元（300,310,320）和从随机数数据/ CRC生成单元（100）和数据比较单元（300,310,320）生成的CRC。

公开(公告)号：KR1020070061082A

公开(公告)日：2007-06-13

申请号：KR1020060043472

申请日：2006-05-15

Applicant: 한국전자통신연구원

Inventor： 정희상 ,  윤병호 ,  박형준

IPC: H04L27/26

CPC classification number: H04L27/2627 ,  H04L5/0053

Abstract: An apparatus and a method for controlling a time offset of a modulator for an OFDM(Orthogonal Frequency Division Multiplexing) system are provided to prevent loss of important data by controlling a time for applying the time offset according to increase and decrease in the time offset. A method for controlling a time offset of a modulator for an OFDM system includes the steps of: collecting, comparing, and determining importance of first data currently transmitted and importance of second data to be transmitted in the future; comparing a first time offset value of the first data and a second time offset value of the second data; and transmitting the second data by controlling the time offset of the second data based on the result value of the importance of the compared and determined first and second data and the compared first and second time offset values.

Abstract translation: 提供了一种用于控制用于OFDM（正交频分复用）系统的调制器的时间偏移的装置和方法，以通过根据时间偏移的增减来控制应用时间偏移的时间来防止重要数据的丢失。 用于控制OFDM系统的调制器的时间偏移的方法包括以下步骤：收集，比较和确定当前发送的第一数据的重要性以及将来要发送的第二数据的重要性; 比较第一数据的第一时间偏移值和第二数据的第二时间偏移值; 以及通过基于比较和确定的第一和第二数据以及所比较的第一和第二时间偏移值的重要性的结果值来控制第二数据的时间偏移来发送第二数据。

公开(公告)号：KR100645388B1

公开(公告)日：2006-11-14

申请号：KR1020050115419

申请日：2005-11-30

Applicant: 한국전자통신연구원

Inventor： 김영섭 ,  박형준

IPC: H04L1/16 ,  H04L1/12

Abstract: A parallel cyclic redundancy check generator and a method to perform a parallel processing of an arbitrary size are provided to perform a parallel process with an arbitrary size by generating a CRC code and integrating the performed CRC calculation. In a parallel cyclic redundancy check generator, a first parallel CRC calculation unit(520) receives parallel input data and calculates the CRC by using a parallel process data size and a CRC code size. A second parallel CRC calculation unit(530) calculates the CRC by using a final parallel input data size and the CRC code size. A register input control multiplexer(516) stores the output of the first CRC calculation unit(520) before the final parallel input data is inputted and controls the stored result information after the output of the second parallel CRC calculation unit(530) is stored. And, an output control multiplexer(515) outputs the parallel input data to parallel output data when the CRC calculation is performed, and outputs the output of the register input control multiplexer(516) when the CRC calculation is finished.

Abstract translation: 提供了并行循环冗余校验生成器和执行任意大小的并行处理的方法，以通过生成CRC码并对执行的CRC计算进行积分来执行具有任意大小的并行处理。 在并行循环冗余校验生成器中，第一并行CRC计算单元（520）接收并行输入数据并通过使用并行处理数据大小和CRC码大小来计算CRC。 第二并行CRC计算单元（530）通过使用最终的并行输入数据大小和CRC码大小来计算CRC。 寄存器输入控制多路复用器（516）在输入最终的并行输入数据之前存储第一CRC计算单元（520）的输出，并且在第二并行CRC计算单元（530）的输出被存储之后控制存储的结果信息。 并且，当CRC计算被执行时，输出控制多路复用器（515）将并行输入数据输出到并行输出数据，并且当CRC计算完成时输出寄存器输入控制多路复用器（516）的输出。