公开(公告)号：JP2009135568A

公开(公告)日：2009-06-18

申请号：JP2007307521

申请日：2007-11-28

Applicant: Denso Corp ,  株式会社デンソー

Inventor： WATANABE TAKAMOTO ,  YAMAUCHI SHIGENORI

IPC: H03K5/13 ,  H03M1/50

CPC classification number: H03K5/133

Abstract: PROBLEM TO BE SOLVED: To provide a pulse delay circuit capable of improving performance of an A/D conversion circuit and a time measurement circuit without depending on sophistication of process technology; its drive method; and an A/D conversion circuit and a time measurement circuit using it. SOLUTION: An inverter circuit INV configuring a delay unit DU is a so-called CMOS transistor comprising a PMOS transistor Tp and an NMOS transistor Tn of which the gates G are interconnected with each other and the drains D are interconnected with each other. The source S and a back gate B of the NMOS transistor Tn are connected to a negative electrode drive terminal 105 (that is the ground). The source S of the PMOS transistor Tp is connected to a positive electrode drive terminal 103 (that is, an analog input signal Vin is applied thereto). The back gate B of the PMOS transistor Tp is connected to a control terminal 107 (that is, a fixed voltage VDD as a control signal is applied thereto). COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供能够提高A / D转换电路和时间测量电路的性能而不依赖于工艺技术的复杂性的脉冲延迟电路; 其驱动方式; A / D转换电路和使用它的时间测量电路。 解决方案：构成延迟单元DU的反相器电路INV是所谓的CMOS晶体管，其包括PMOS晶体管Tp和NMOS晶体管Tn，栅极G彼此互连并且漏极D彼此互连 。 NMOS晶体管Tn的源极S和背栅极B连接到负极驱动端子105（即接地）。 PMOS晶体管Tp的源极S连接到正极驱动端子103（即，向其施加模拟输入信号Vin）。 PMOS晶体管Tp的背栅极B连接到控制端子107（即，施加控制信号的固定电压VDD）。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007205854A

公开(公告)日：2007-08-16

申请号：JP2006024670

申请日：2006-02-01

Applicant: Denso Corp ,  Jeco Co Ltd ,  ジェコー株式会社 ,  株式会社デンソー

Inventor： WATANABE TAKAMOTO ,  MASUDA SUMIO

IPC: G04G5/00 ,  G04R20/00 ,  G04R20/12 ,  H03D1/22

CPC classification number: H04L27/066 ,  G04R20/12 ,  H04L2027/003 ,  H04L2027/0046

Abstract: PROBLEM TO BE SOLVED: To provide a radio controlled clock which verifies time information reconstructed from standard radio wave in a short period of time. SOLUTION: Regarding the phase ϕ N, m of a carrier wave (carrier) of a long-wave standard radio wave calculated by a phase arithmetic circuit 23, based on the same phase component and orthogonal component generated by an orthogonal detection circuit 18, a dispersion arithmetic circuit 24 finds the dispersion from the reference phase varying at a time variation proportional to the error ε of a reference signal CK2. When the dispersion is an allowance or less, a time verifying circuit 26 determines that the receiving state (S/N) of the carrier is good, and determines the possibility of correction of the clock time according to the verifying result of the time information obtained from a single frame. When the dispersion is more than the allowance, the time verifying circuit 26 determines that the receiving state of the carrier is bad, and prohibits the correction of the clock time regardless of the verifying result of the time information. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在短时间内验证从标准无线电波重建的时间信息的无线电控制时钟。 解决方案：关于由相位运算电路23计算的长波标准无线电波的载波（载波）的相位φSB，N，m，基于相同的相位分量和正交 通过正交检测电路18生成的分量，色散运算电路24根据与基准信号CK2的误差ε成比例的时间变化，求出基准相位的色散。 当色散为允许值以下时，时间验证电路26确定载波的接收状态（S / N）良好，并且根据获得的时间信息的验证结果确定时钟时间的校正的可能性 从一个框架。 当色散大于允许时，时间验证电路26确定载波的接收状态不良，并且不管时间信息的验证结果如何，都禁止时钟时间的校正。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007006368A

公开(公告)日：2007-01-11

申请号：JP2005186850

申请日：2005-06-27

Applicant: Denso Corp ,  株式会社デンソー

Inventor： WATANABE TAKAMOTO

IPC: H03M1/12 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092

CPC classification number: H03M1/0612 ,  H03M1/145 ,  H03M1/207 ,  H03M1/502 ,  H03M1/60

Abstract: PROBLEM TO BE SOLVED: To provide an A/D conversion circuit in a TAD system whose characteristics are stable for suppressing the influence of any working error or fine dust relatively increasing according to the microfabrication of a CMOS manufacturing process.
SOLUTION: A transistor (see figure (a)) configuring a pulse delay circuit is compared with a transistor (see (b)) configuring a latch & encoder 12, and transistor length (pattern width of gate Gp, Gn) L is designed so as to be doubled (that is, the minimum line width of a design rule is doubled), and the transistor width is designed so as to be doubled. In this case, a contact window Co as the connection point of a wiring pattern is formed of the minimum line width in any circuit, and the pattern width (width in a direction following transistor length L) of drains Dp, Dn or sources Sp, Sn whose size is specified according to the size of the contact window Co is designed so as to be turned into the necessary minimum size.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种TAD系统中的A / D转换电路，其特性是稳定的，以根据CMOS制造工艺的微细加工来抑制任何工作误差或细粉尘的相对增加的影响。 将构成脉冲延迟电路的晶体管（参见图（a））与构成锁存器和编码器12的晶体管（参见（b））和晶体管长度（栅极Gp，Gn的图案宽度）L 被设计成加倍（即，设计规则的最小线宽加倍），并且晶体管宽度被设计成加倍。 在这种情况下，作为布线图案的连接点的接触窗口Co由任何电路中的最小线宽以及排水口Dp，Dn或源Sp的图案宽度（沿着晶体管长度L的方向的宽度）形成， 根据接触窗Co的尺寸规定尺寸的Sn被设计为变成必要的最小尺寸。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005094341A

公开(公告)日：2005-04-07

申请号：JP2003324823

申请日：2003-09-17

Applicant: Denso Corp ,  株式会社デンソー

Inventor： TERASAWA TOMOHITO ,  WATANABE TAKAMOTO

IPC: H03M1/64 ,  H03M1/00 ,  H03M1/06 ,  H03M1/14 ,  H03M1/50

CPC classification number: H03M1/06 ,  G04F10/005 ,  H03M1/14 ,  H03M1/502 ,  H03M1/60

Abstract: PROBLEM TO BE SOLVED: To reduce the power consumption of an A/D conversion circuit using a pulse delay circuit. SOLUTION: This A/D conversion circuit 1 is provided with a ring gate delay circuit (RGD) 10 obtained by connecting inversion circuits in a ring shape as a pulse delay circuit, and in the RGD 10, the voltage signal Vin of an A/D conversion object is applied as power supply voltage and the circling time of a pulse signal changes in accordance with the voltage signal Vin. Then, an encoding processing block 3 detects the number of stages of inversion circuits where a pulse signal has passed through in the RGD 10 within a certain set time, data DO1 representing the number of stages is outputted as an A/D conversion result of the voltage signal Vin, but especially, the input ranges of power supply voltage VDDL of the encoding processing block 3 and the voltage signal Vin are set equal to or below (¾ Vthn ¾ + ¾ Vthp ¾). In addition, the Vthn and Vthp are respective threshold voltages of an n channel transistor and a p channel transistor of gate circuits constituting circuits 3 and 10. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了降低使用脉冲延迟电路的A / D转换电路的功耗。 解决方案：该A / D转换电路1设置有通过连接作为脉冲延迟电路的环形反转电路而获得的环形栅极延迟电路（RGD）10，并且在RGD 10中，电压信号Vin 应用A / D转换对象作为电源电压，并且脉冲信号的循环时间根据电压信号Vin而变化。 然后，编码处理块3在一定的设定时间内检测在RGD10中已经通过了脉冲信号的反相电路的级数，表示级数的数据DO1作为A / D转换结果输出 电压信号Vin，但是特别地，编码处理块3的电源电压VDDL和电压信号Vin的输入范围被设定为等于或小于（¾Vthn¾+¾Vthp¾）。 另外，Vthn和Vthp分别是构成电路3和10的栅极电路的n沟道晶体管和p沟道晶体管的阈值电压。（C）2005，JPO和NCIPI

公开(公告)号：JP2003046390A

公开(公告)日：2003-02-14

申请号：JP2001231675

申请日：2001-07-31

Applicant: Denso Corp ,  株式会社デンソー

Inventor： MIZUNO TAMOTSU ,  WATANABE TAKAMOTO

IPC: H03M1/12 ,  H03H17/06 ,  H03M1/06 ,  H03M1/14 ,  H03M1/50

CPC classification number: H03M1/0626 ,  G04F10/005 ,  H03M1/14 ,  H03M1/502 ,  H03M1/60

Abstract: PROBLEM TO BE SOLVED: To provide a filtering method by which an unnecessary high frequency signal component unable to be eliminated by a digital moving average filter can be attenuated without the need for a CR filter and to provide an analog/ digital converter with a filtering function. SOLUTION: An analog moving average filter 2 is provided to a first stage of the analog/digital converter provided with an analog/digital converter 4 and a high frequency signal component eliminating digital moving average filter 6, and sampling frequencies of the filters 6, 2 are set to be fsd=n×fsa (n is a positive integer: 1, 2, etc.). As a result, an unnecessary signal pass band from the filter 6 appearing at frequencies of a multiple of n of the sampling frequency fsd is overlapped with a region with an infinite attenuation appearing at frequencies of a multiple of n of the sampling frequency fsa at the filter 2 and the entire device can efficiently attenuate the unnecessary high frequency signal component. Further, the similar effect can be obtained by using a temporal analog/digital converter in place of the analog moving average filter 2 and the analog/digital converter 4.

Abstract translation: 要解决的问题：提供一种滤波方法，通过该方法，可以在不需要CR滤波器的情况下衰减不能被数字移动平均滤波器消除的不必要的高频信号分量，并且提供具有滤波功能的模拟/数字转换器 。 解决方案：将模拟移动平均滤波器2提供给设置有模拟/数字转换器4的模/数转换器的第一级和消除数字移动平均滤波器6的高频信号分量，以及滤波器6,2的采样频率 被设置为fsd = n×fsa（n是正整数：1,2等）。 结果，出现在采样频率fsd的n的倍数的频率处的滤波器6的不必要的信号通带与在采样频率fsa的n倍的频率处出现无穷衰减的区域重叠 滤波器2和整个器件可以有效地衰减不必要的高频信号分量。 此外，通过使用时间模拟/数字转换器代替模拟移动平均滤波器2和模拟/数字转换器4可以获得类似的效果。

公开(公告)号：JP2002271181A

公开(公告)日：2002-09-20

申请号：JP2001072141

申请日：2001-03-14

Applicant: DENSO CORP

Inventor： WATANABE TAKAMOTO ,  ISOMURA HIROBUMI

IPC: G06F1/06 ,  G01S17/10 ,  G06F1/04 ,  H03K5/131 ,  H03K5/14 ,  H03K5/15 ,  H03L7/00

Abstract: PROBLEM TO BE SOLVED: To provide a shift clock generating unit, which is capable of generating shift clock that is shifted from a reference clock by a prescribed phase difference, without using the clock that has a period which corresponds to the phase difference. SOLUTION: A shift clock generating unit 20 is equipped with delay lines connected to delay units 80(1) to 80(k) composed of gate circuits, switches SWb to SWh connected to the outputs of the delay units, and decoders 90b to 90h which take out shift clocks CKb to CKh obtained by delaying the reference clock by a desired time, by turning on a specific switch from among the switches SWb to SWh. Control data CD used for enabling the reference clock generating unit (digital PLL) to generate the reference clock are inputted into the decoders as period data CD representing the period of the reference clock MCK, and the decoders decide a specific switch selected from among the switch group to be turned, on the basis of the period data.

公开(公告)号：JPH11355109A

公开(公告)日：1999-12-24

申请号：JP33720298

申请日：1998-11-27

Applicant: DENSO CORP

Inventor： YAMAUCHI SHIGENORI ,  WATANABE TAKAMOTO

IPC: H03K5/13 ,  H03K5/131 ,  H03K5/14 ,  H03K5/26 ,  H03K19/0948 ,  H03L7/06 ,  H03M1/50

Abstract: PROBLEM TO BE SOLVED: To attain the coincidence of time resolution at every pulse generating circuit when the plural pulse generating circuits respectively generate a pulse signal by a prescribed timing through the use of delay signals which are successively outputted from the prescribed connection point of delay elements. SOLUTION: The pulse signals P1 are successively outputted from one digital control oscillation circuit 64 by a fixed period corresponding to control data Da and the pulse signals P2 where a phase is deviated as against the period are successively outputted from the other digital control oscillation circuit 66 by the period being the same as that of the pulse signal P1. The pulse signal P0 with a duty ratio corresponding to the deviation of the phases of the pulse signals P1 and P2 is outputted from an RS flip-flop 68. Since the respective digital control oscillation circuits 64 and 66 share a ring oscillator 62, their time resolutions perfectly coincide each other and the period of the pulse signal P0 from the RS flip-flop 68 and the duty ratio are controlled with high precision.

公开(公告)号：JPH09218281A

公开(公告)日：1997-08-19

申请号：JP2432496

申请日：1996-02-09

Applicant: DENSO CORP

Inventor： WATANABE TAKAMOTO ,  YAMAUCHI SHIGENORI ,  HOASHI YOSHIAKI

IPC: G04F10/04 ,  G01R29/02 ,  H03K5/15 ,  H03K5/26 ,  H03K21/00

Abstract: PROBLEM TO BE SOLVED: To provide a time measuring apparatus which can measure a time interval between each of a plurality of signals to be measured and a measurement reference signal and hold each measuring result even when the plurality of signals are generated at considerably close time points each other. SOLUTION: The apparatus is provided with four signal-processing parts 6a-6d. Each processing part 6a-6d takes in a delay signal DY0-DYn output in accordance with a transmission position of a measurement start signal PA from a signal delay line 4 which delays and transmits the measurement start signal PA, with a timing of a measurement end signal PBi (i=1-4), and outputs digital data corresponding to a time interval of the signals PA and PBi as a measuring value DAi. Since the signal PBi and measuring value DAi are input/output through respective individual signal lines, the signals PBi never interfere with each other at however close time points the signals PBi are generated. Neither the measuring value DAi is rewritten subsequent to a succeeding measurement.

公开(公告)号：JPH0936387A

公开(公告)日：1997-02-07

申请号：JP20538795

申请日：1995-07-18

Applicant: DENSO CORP

Inventor： KARESUE SHIYOUWA ,  AO KENICHI ,  UENOYAMA HIROBUMI ,  SUZUKI YASUTOSHI ,  YAMADA TOSHITAKA ,  OTA TAMEJI ,  WATANABE TAKAMOTO ,  TAKEUCHI YUKIHIRO

IPC: G01L1/18 ,  G01P15/125 ,  H01L21/26 ,  H01L21/316 ,  H01L21/318 ,  H01L29/84

Abstract: PROBLEM TO BE SOLVED: To easily eliminate an electron which is trapped by the interface of two insulation films by applying such electromagnetic wave as ultraviolet ray to the interface between a second insulation film and a first insulation film in a process after the second insulation film is formed. SOLUTION: Ion is implanted to a specific region of a silicon substrate 10 to form a drain region 11, a source region 12, and conductive layers 17 and 18. Then, only a sacrifice layer is eliminated by etching and 5,000Å gap 20 is formed between a movable member 15 and the surface of the silicon substrate 10. At this time, Si3 N4 film 14 prevents SiO2 film 13 from being etched. Then, ultraviolet rays are uniformly applied to the surface of the Si3 N4 film 14 for at least 40 minutes via the movable member 15 using a mercury lamp. When the Si3 N4 film 14 is 500Å thick, an electron which is trapped at an interface level can be completely eliminated by applying ultraviolet rays for at least 40 minutes.

公开(公告)号：JP2015021782A

公开(公告)日：2015-02-02

申请号：JP2013148539

申请日：2013-07-17

Applicant: 株式会社デンソー ,  Denso Corp

Inventor： YAMAUCHI SHIGENORI ,  WATANABE TAKAMOTO ,  TAGUCHI NOBUYUKI

IPC: G01C19/5726 ,  G01C19/5747 ,  H01L29/84

Abstract: 【課題】PWM駆動信号によって試験体を振動させる加振装置において、ノイズによる影響を軽減できるようにする。【解決手段】ジャイロセンサにおいてADC57は、振動子11の振動波形の振幅に応じた振幅デジタル値を生成するとともに、2つの異なる基準電圧の差に応じた電圧デジタル値を生成する。そして、駆動回路50(TDC51除く)は、電圧デジタル値と振幅デジタル値との比が一定になるよう駆動信号を生成する。このようなジャイロセンサによれば、基準電圧の差(電圧デジタル値)と振動波形の振幅に応じた振幅デジタル値との比が一定になるよう駆動信号を生成するので、A/D変換を行う構成が温度等の環境の影響を受ける場合であっても、適切な駆動信号を生成することができる。【選択図】図5

Abstract translation: 要解决的问题：提供一种用于激发测试片的激励装置，其具有可以减少噪声影响的脉宽调制（PWM）驱动信号。解答：在陀螺仪传感器中，A / D转换器（ADC）57产生 振幅数字值对应于振动器11的振动波形的振幅，并且产生与两个不同参考电压之间的差对应的电压数字值。 然后，驱动电路50（时间到数字转换器（TDC）51除外）产生驱动信号，使得电压数字值与振幅数字值的比率是恒定的。 根据这种陀螺传感器，产生驱动信号，使得参考电压（电压数字值）与对应于振动波形振幅的振幅数字值之间的差值的比率是恒定的，因此适当的驱动信号 即使在进行A / D转换的结构受温度等环境的影响的情况下也能够生成。