公开(公告)号：US20220181166A1

公开(公告)日：2022-06-09

申请号：US17677105

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Robert May ,  Sri Ranga Sai Boyapati ,  Srinivas V. Pietambaram ,  Chung Kwang Christopher Tan ,  Aleksandar Aleksov

IPC: H01L21/48 ,  H01L23/498

Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.

公开(公告)号：US11348882B2

公开(公告)日：2022-05-31

申请号：US16683125

申请日：2019-11-13

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Johanna M. Swan ,  Adel A. Elsherbini ,  Veronica Aleman Strong

IPC: H01L23/60 ,  H01L23/498 ,  H01L23/053 ,  H01L23/00

Abstract: Embodiments may relate to a microelectronic package with an electrostatic discharge (ESD) protection structure within the package substrate. The ESD protection structure may include a cavity that has a contact of a signal line and a contact of a ground line positioned therein. Other embodiments may be described or claimed.

公开(公告)号：US11309619B2

公开(公告)日：2022-04-19

申请号：US16327811

申请日：2016-09-23

Applicant: INTEL CORPORATION

Inventor： Sasha Oster ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Adel Elsherbini ,  Shawna Liff ,  Aleksandar Aleksov ,  Johanna Swan

IPC: H01L23/66 ,  H01Q1/22 ,  H01Q21/06 ,  H01Q21/00 ,  H01P5/18

Abstract: A waveguide coupling system may include at least one waveguide member retention structure disposed on an exterior surface of a semiconductor package. The waveguide member retention structure may be disposed a defined distance or at a defined location with respect to an antenna carried by the semiconductor package. The waveguide member retention structure may engage and guide a waveguide member slidably inserted into the respective waveguide member retention structure. The waveguide member retention structure may position the waveguide member at a defined location with respect to the antenna to maximize the power transfer from the antenna to the waveguide member.

公开(公告)号：US11296040B2

公开(公告)日：2022-04-05

申请号：US16721442

申请日：2019-12-19

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Feras Eid ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Veronica Aleman Strong

IPC: H01L21/00 ,  H01L23/60 ,  H01L23/48 ,  H01L27/02 ,  H01L23/00 ,  H01L23/498

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.

公开(公告)号：US20220093561A1

公开(公告)日：2022-03-24

申请号：US17025709

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel A. Elsherbini ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/00

Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.

公开(公告)号：US20220093546A1

公开(公告)日：2022-03-24

申请号：US17025181

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Kevin P. O'Brien ,  Kimin Jun ,  Han Wui Then ,  Mohammad Enamul Kabir ,  Gerald S. Pasdast ,  Feras Eid ,  Aleksandar Aleksov ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L49/02 ,  H01L25/065

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

公开(公告)号：US20220093517A1

公开(公告)日：2022-03-24

申请号：US17025166

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid ,  Randy B. Osborne ,  Van H. Le

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/49

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include an interposer, including an organic dielectric material, and a microelectronic component coupled to the interposer by direct bonding.

公开(公告)号：US11222856B2

公开(公告)日：2022-01-11

申请号：US16721603

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Feras Eid ,  Veronica Aleman Strong ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/60 ,  H01L21/48 ,  H01L49/00 ,  H01L23/498 ,  H01H61/01 ,  H01H49/00 ,  H01H61/00 ,  H01L23/00

Abstract: Embodiments may relate to a package substrate that includes a signal line and a ground line. The package substrate may further include a switch communicatively coupled with the ground line. The switch may have an open position where the switch is communicatively decoupled with the signal line, and a closed position where the switch is communicatively coupled with the signal line. Other embodiments may be described or claimed.

公开(公告)号：US20210358855A1

公开(公告)日：2021-11-18

申请号：US17388964

申请日：2021-07-29

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Henning Braunisch ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/538 ,  H05K1/18 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48

Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.

公开(公告)号：US11101205B2

公开(公告)日：2021-08-24

申请号：US16564168

申请日：2019-09-09

Applicant: Intel Corporation

Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

IPC: H01L23/498 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68

Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.