公开(公告)号：US09349636B2

公开(公告)日：2016-05-24

申请号：US14038502

申请日：2013-09-26

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  James S. Clarke

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L21/76849 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L2224/45015 ,  H01L2924/0002 ,  H01L2924/00011 ,  H01L2924/00

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

Abstract translation: 介电层及其形成方法。 限定在介电层中的开口和沉积在开口内的电线，其中所述电线包括由护套材料围绕的芯材料，其中所述护套材料表现出第一电阻率1，并且所述芯材料表现出第二电阻率 和＆rgr; 2小于＆rgr; 1。