公开(公告)号：US09977618B2

公开(公告)日：2018-05-22

申请号：US14142697

申请日：2013-12-27

Applicant: INTEL CORPORATION

Inventor： Debendra Das Sharma ,  Mohan J. Kumar ,  Balint Fleischer

IPC: G06F12/00 ,  G06F3/06 ,  G06F9/50

CPC classification number: G06F3/0644 ,  G06F3/0607 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/067 ,  G06F3/0679 ,  G06F9/5016 ,  G06F2209/5011

Abstract: An apparatus for pooling memory resources across multiple nodes is described herein. The apparatus includes a shared memory controller, wherein each node of the multiple nodes is connected to the shared memory controller. The apparatus also includes a pool of memory connected to the shared memory controller, wherein a portion of the pool of memory is allocated to each node of the multiple nodes.

公开(公告)号：US20180006809A1

公开(公告)日：2018-01-04

申请号：US15200604

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Vincent R. Scarlata ,  Francis X. McKeen ,  Carlos V. Rozas ,  Simon P. Johnson ,  Bo Zhang ,  Mona Vij ,  Brandon Baker ,  Mohan J. Kumar ,  Asit K. Mallick ,  Mark A. Gentry ,  Somnath Chakrabarti

IPC: H04L9/08 ,  H04L29/06 ,  G06F21/62

CPC classification number: H04L9/0816 ,  G06F21/6218 ,  H04L9/0861 ,  H04L9/088 ,  H04L9/0894 ,  H04L9/14 ,  H04L63/06

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to store data in a secure domain in a cloud network, create encryption keys, where each encryption key is to provide a different type of access to the data, and store the encryption keys in a secure domain key store in the cloud network. In an example, each encryption key provides access to a different version of the data. In another example, a counter engine stores the location of each version of the data in the cloud network.

公开(公告)号：US09753793B2

公开(公告)日：2017-09-05

申请号：US14319387

申请日：2014-06-30

Applicant: INTEL CORPORATION

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Camille C. Raad

IPC: G06F11/07 ,  G09C1/00 ,  G11C29/52 ,  G11C5/04 ,  G11C29/04

CPC classification number: G06F11/073 ,  G06F11/0769 ,  G06F11/0787 ,  G09C1/00 ,  G11C5/04 ,  G11C29/52 ,  G11C2029/0409

Abstract: Examples may include a basic input/output system (BIOS) for a computing platform communicating with a controller for a non-volatile dual in-line memory module (NVDIMM). Communication between the BIOS and the controller may include a request for the controller to scan and identify error locations in non-volatile memory at the NVDIMM. The non-volatile memory may be capable of providing persistent memory for the NVDIMM.

公开(公告)号：US20170123872A1

公开(公告)日：2017-05-04

申请号：US14925131

申请日：2015-10-28

Applicant: Intel Corporation

Inventor： Theodros Yigzaw ,  Mohan J. Kumar ,  Hisham Shafi ,  Ron Gabor ,  Ashok Raj

IPC: G06F11/07 ,  G06F9/30

CPC classification number: G06F11/079 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/3016 ,  G06F11/0721 ,  G06F11/0784 ,  G06F11/0787 ,  G06F11/0793 ,  G06F12/00 ,  G06F12/0246

Abstract: In one embodiment, a processor includes a core having a fetch unit to fetch instructions, a decode unit to decode the instructions, and one or more execution units to execute the instructions. The core may further include: a first pair of block address range registers to store a start location and an end location of a block range within a non-volatile block storage coupled to the processor; and a block status storage to store an error indicator responsive to an occurrence of an error within the block range during a block operation. Other embodiments are described and claimed.

公开(公告)号：US09383932B2

公开(公告)日：2016-07-05

申请号：US14142733

申请日：2013-12-27

Applicant: INTEL CORPORATION

Inventor： Debendra Das Sharma ,  Mohan J. Kumar ,  Balint T. Fleischer

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/20 ,  G06F13/32

CPC classification number: G06F9/52 ,  G06F3/0619 ,  G06F3/0661 ,  G06F3/0688 ,  G06F9/467 ,  G06F11/2017 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/1081 ,  G06F13/1663 ,  G06F13/32 ,  G06F13/4022 ,  G06F2212/1056 ,  G11C14/009

Abstract: An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.

Abstract translation: 这里描述了一种用于提供数据一致性的装置。 该装置包括全局持久存储器。 使用包含输入/输出（I / O）语义和内存语义的协议来访问全局永久存储器。 该装置还包括反射存储区域。 反射的存储器区域是全局持久存储器的一部分，并且多个节点的每个节点将反射的存储器区域映射到不可高速缓存的空间中。 此外，该装置包括信号量存储器。 信号量存储器为强制数据一致性提供硬件辅助。

公开(公告)号：US20160087847A1

公开(公告)日：2016-03-24

申请号：US14494892

申请日：2014-09-24

Applicant: INTEL CORPORATION

Inventor： Ramamurthy Krithivas ,  Narayan Ranganathan ,  Mohan J. Kumar ,  John C. Leung

IPC: H04L12/24 ,  H04L12/855 ,  H04L29/12

CPC classification number: H04L41/12 ,  H04L41/044 ,  H04L47/2466 ,  H04L61/2015 ,  H04L61/2507

Abstract: Mechanisms to enable management controllers to learn the control plane hierarchy in data center environments. The data center is configured in a physical hierarchy including multiple pods, racks, trays, and sleds and associated switches. Management controllers at various levels in a control plane hierarchy and associated with switches in the physical hierarchy are configured to add their IP addresses to DHCP (Dynamic Host Control Protocol) responses that are generated by a DCHP server in response to DCHP requests for IP address requests initiated by DHCP clients including manageability controllers, compute nodes and storage nodes in the data center. As the DCHP response traverses each of multiple switches along a forwarding path from the DCHP server to the DHCP client, an IP address of the manageability controller associated with the switch is inserted. Upon receipt at the DHCP client, the inserted IP addresses are extracted and used to automate learning of the control plane hierarchy.

Abstract translation: 允许管理控制器在数据中心环境中学习控制平面层次的机制。 数据中心配置在物理层次结构中，包括多个pod，rack，tray以及sleds和关联的switch。 配置在控制平面层级中并与物理层次结构中的交换机相关联的管理控制器被配置为将其IP地址添加到由DCHP服务器响应于对于IP地址请求的DCHP请求而产生的DHCP（动态主机控制协议）响应 由DHCP客户端启动，包括数据中心中的可管理性控制器，计算节点和存储节点。 随着DCHP响应遍历从DCHP服务器到DHCP客户端的转发路径的多个交换机中的每一个，插入与交换机相关联的可管理性控制器的IP地址。 在DHCP客户端收到后，插入的IP地址被提取并用于自动化控制平面层次结构的学习。

公开(公告)号：US20160085965A1

公开(公告)日：2016-03-24

申请号：US14964020

申请日：2015-12-09

Applicant: Intel Corporation

Inventor： Shamanna M. Datta ,  Mohan J. Kumar

IPC: G06F21/53 ,  G06F21/85 ,  G06F21/74

CPC classification number: G06F21/53 ,  G06F21/00 ,  G06F21/74 ,  G06F21/85

Abstract: Methods and apparatus for initiating secure operations in a microprocessor system are described. In one embodiment, a system includes a processor to execute a secured enter instruction, and a chipset to cause the system to enter a quiescent state during execution of the secured enter instruction.

公开(公告)号：US09230116B2

公开(公告)日：2016-01-05

申请号：US13837640

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Shamanna M. Datta ,  Mohan J. Kumar

IPC: G06F21/57 ,  G06F21/60

CPC classification number: G06F21/60 ,  G06F21/57

Abstract: A technique to verify firmware. One embodiment of the invention uses a processor's micro-code to verify a system's firmware, such that the firmware can be included in a trusted chain of code along with the operating system.

公开(公告)号：US11960900B2

公开(公告)日：2024-04-16

申请号：US16729321

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Rajat Agarwal ,  Mohan J. Kumar

IPC: G06F9/44 ,  G06F9/4401 ,  G06F9/445

CPC classification number: G06F9/4403 ,  G06F9/445

Abstract: Technologies for fast boot-up of a compute device with error-correcting code (ECC) memory are disclosed. A basic input/output system (BIOS) of a compute device may assign memory addresses of the ECC memory to different processors on the compute device. The processors may then initialize the ECC memory in parallel by writing to the ECC memory. The processors may write to the ECC memory with direct-store operations that are immediately written to the ECC memory instead of being cached. The BIOS may continue to operation on one processor while the rest of the processors initialize the ECC memory.

公开(公告)号：US11893379B2

公开(公告)日：2024-02-06

申请号：US16995934

申请日：2020-08-18

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Deepak Gandiga Shivakumar ,  Dan Williams ,  Tiffany Kasanicky ,  Krzysztof Rusocki ,  Nicholas Moulin ,  Mohan J. Kumar

IPC: G06F8/654 ,  G06F8/656 ,  G06F9/4401 ,  G06F9/48

CPC classification number: G06F8/654 ,  G06F8/656 ,  G06F9/4401 ,  G06F9/4881

Abstract: Systems, apparatuses and methods may provide for technology that exchanges activation information between system firmware and an operating system (OS), wherein the activation information includes one or more of status information, activation state information, capability information, activation time information or quiesce time information. The technology also conducts a runtime upgrade of the device firmware based on the activation information, wherein the runtime upgrade bypasses a reboot of the computing system.