公开(公告)号：US20190147640A1

公开(公告)日：2019-05-16

申请号：US16173722

申请日：2018-10-29

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer KP ,  Jonathan Kennedy ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Tomer Bar-On ,  Carsten Benthin ,  Adam T. Lake ,  Vasanth Ranganathan ,  Abhishek R. Appu

IPC: G06T15/08 ,  H04N5/369 ,  G06T15/00 ,  G06T15/60 ,  G06T15/10 ,  H04N5/232 ,  H04N13/239 ,  H04N13/344 ,  G06K9/00 ,  G02B27/01

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

公开(公告)号：US20190096024A1

公开(公告)日：2019-03-28

申请号：US15716280

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Altug Koker ,  Vasanth Ranganathan

IPC: G06T1/20 ,  G06F12/0875 ,  G06F12/1045 ,  G06F9/30 ,  G06T1/60 ,  G06T15/00

Abstract: Embodiments are generally directed to area-efficient implementations of graphics instructions. An embodiment of an apparatus includes a graphics subsystem, the graphics subsystem including one or more of a first logic for processing of memory read-return data for single-instruction-multiple-data instructions, the first logic to store data for a message in raw data format and delay conversion into shader format until all cache line requests for the message have been received; a second logic for assembly of memory read-return data for media block instructions into shader register format, the logic to provide for storage of valid bytes from a cache fragment in a register; or a third logic to remap scatter or gather instructions to untyped surface instruction types. An embodiment of an apparatus includes a graphics subsystem, the graphics subsystem including a translation lookaside buffer (TLB) and a data port controller to control the TLB, the data port controller including an incoming request pipeline to receive an incoming request with virtual address and generate a response, an incoming response pipeline to receive the response and generate a cache request, and an invalidation flow pipeline.

公开(公告)号：US10134115B2

公开(公告)日：2018-11-20

申请号：US15488619

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Prasoonkumar Surti ,  Joydeep Ray ,  Michael J. Norris

IPC: G06T15/00 ,  G06T5/00 ,  G06T1/20 ,  G06T1/60 ,  G06T11/00

Abstract: One embodiment provides for a general-purpose graphics processor comprising a fragment processing unit configured to generate pixel color data in a graphics processing pipeline, the fragment processing unit output color data to a multisample render target; and a memory allocator to allocate memory to store color data associated with the multisample render target, the memory allocator to merge a memory allocation for multiple pixels having a sample associated with equal color data.

公开(公告)号：US20180314250A1

公开(公告)日：2018-11-01

申请号：US15581133

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Brian T. Lewis ,  Feng Chen ,  Jeffrey R. Jackson ,  Justin E. Gottschlich ,  Rajkishore Barik ,  Xiaoming Chen ,  Prasoonkumar Surti ,  Mike B. Macpherson ,  Murali Sundaresan

IPC: G05D1/00 ,  G06N3/04 ,  G06N3/08 ,  G06N3/063

CPC classification number: G06N3/063 ,  B60W30/095 ,  G01C21/34 ,  G06N3/008 ,  G06N3/0454

Abstract: A mechanism is described for facilitating smart collection of data and smart management of autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and combining a first computation directed to be performed locally at a local computing device with a second computation directed to be performed remotely at a remote computing device in communication with the local computing device over the one or more networks, where the first computation consumes low power, wherein the second computation consumes high power.

公开(公告)号：US20180308450A1

公开(公告)日：2018-10-25

申请号：US15493606

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Eric J. Hoekstra ,  Subramaniam Maiyuran ,  Prasoonkumar Surti ,  Eric G. Liskay ,  Joydeep Ray ,  Michael J. Norris ,  Wenyin Fu ,  Altug Koker

IPC: G09G5/02

CPC classification number: G09G5/02 ,  G09G2340/06 ,  G09G2350/00

Abstract: Methods and apparatus relating to techniques for provision of color mapping for better compression ratio are described. In an embodiment, a plurality of bits are moved from all channels of a first Red Green Blue Alpha (RGBA) space to an alpha channel of a second RGBA space. The plurality of the bits are selected from higher order bits of the first RGBA space. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180308208A1

公开(公告)日：2018-10-25

申请号：US15819093

申请日：2017-11-21

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06T1/60 ,  G06F17/16

CPC classification number: G06T1/20 ,  G06F8/41 ,  G06F9/45533 ,  G06F9/5061 ,  G06F9/5094 ,  G06F17/16 ,  G06F2009/45583 ,  G06T1/60

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type

公开(公告)号：US20180307981A1

公开(公告)日：2018-10-25

申请号：US15494826

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Gokcen Cilingir ,  Elmoustapha Ould-Ahmed-Vall ,  Rajkishore Barik ,  Kevin Nealis ,  Xiaoming Chen ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Abhishek R. Appu ,  John C. Weast ,  Sara S. Baghsorkhi ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Nilesh Shah ,  Archie Sharma ,  Mayuresh M. Varerkar

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06F9/46 ,  G06N3/04 ,  G06N3/063 ,  G06T1/20

Abstract: An apparatus to facilitate neural network (NN) training is disclosed. The apparatus includes training logic to receive one or more network constraints and train the NN by automatically determining a best network layout and parameters based on the network constraints.

公开(公告)号：US20180307485A1

公开(公告)日：2018-10-25

申请号：US15493467

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Ramkumar Ravikumar ,  Kiran C. Veernapu ,  Prasoonkumar Surti ,  Vasanth Ranganathan

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G06F13/36 ,  G06F13/40

Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to assemble a general register file (GRF) message and hold the GRF message in storage in a data port until all data for the GRF message is received. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180300933A1

公开(公告)日：2018-10-18

申请号：US15489177

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US20180293961A1

公开(公告)日：2018-10-11

申请号：US15483748

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Atsuo Kuwahara ,  Sameer Kp ,  Jonathan Kennedy

IPC: G09G5/36 ,  G06T15/00 ,  G06T1/60 ,  G09G5/39 ,  G06F13/16

Abstract: Systems and methods may provide for determining a start time for an output image scanner to begin scanning an output image to a display device, determining a processing start time for each row of blocks of image pixel data within a rasterizer to ensure its completion before each row of blocks of image pixel data within the output image begin to be scanned out, and scheduling the start of processing of each row of blocks of image pixel data. In one example, the start time for the rasterizer to process a row of blocks of image pixel data uses the number of graphical objects to rendered into the output image and the processing times required by prior images.