公开(公告)号：EP3396544A1

公开(公告)日：2018-10-31

申请号：EP18163725.7

申请日：2018-03-23

Applicant: INTEL Corporation

Inventor： APPU, Abhishek R. ,  KOKER, Altug ,  WEAST, John C. ,  MACPHERSON, Mike B. ,  KIM, Dukhwan ,  HURD, Linda L. ,  BAGHSORKHI, Sara S. ,  GOTTSCHLICH, Justin E. ,  SURTI, Prasoonkumar ,  SAKTHIVEL, Chandrasekaran ,  RAY, Joydeep

IPC: G06F9/50 ,  G06N3/02

CPC classification number: G06T1/20 ,  G06F9/5061 ,  G06F9/5072 ,  G06N3/02 ,  G06N3/04 ,  H04L67/10

Abstract: A mechanism is described for facilitating sharing of data and compression expansion of models at autonomous machines. A method of embodiments, as described herein, includes detecting a first processor processing information relating to a neural network at a first computing device, where the first processor comprises a first graphics processor and the first computing device comprises a first autonomous machine. The method further includes facilitating the first processor to store one or more portions of the information in a library at a database, where the one or more portions are accessible to a second processor of a computing device.

公开(公告)号：EP3392827A1

公开(公告)日：2018-10-24

申请号：EP18167859.0

申请日：2018-04-17

Applicant: INTEL Corporation

Inventor： VEMBAR, Deepak S. ,  KUWAHARA, Atsuo ,  SAKTHIVEL, Chandrasekaran ,  VENKATARAMAN, Radhakrishnan ,  INSKO, Brent E. ,  KALRA, Anupreet S. ,  LABBE, Hugues ,  KOKER, Altug ,  APODACA, Michael ,  XIAO, Kai ,  BOLES, Jeffrey S. ,  LAKE, Adam T. ,  CIMINI, David M. ,  VEMBU, Balaji ,  OULD-AHMED-VALL, Elmoustapha ,  KWIATKOWSKI, Jacek ,  LAWS, Phillip R. ,  SHAH, Ankur N. ,  APPU, Abhishek R. ,  RAY, Joydeep ,  FU, Wenyin ,  KABURLASOS, Nikos ,  SURTI, Prasoonkumar ,  BOROLE, Bhushan M.

IPC: G06T1/20 ,  G06T15/00 ,  G06T15/20 ,  G06F3/14

CPC classification number: G06F3/1454 ,  G06F3/1431 ,  G06F3/147 ,  G06T1/20 ,  G09G3/003 ,  G09G5/363 ,  G09G2340/02 ,  G09G2350/00 ,  G09G2352/00 ,  G09G2354/00 ,  G09G2360/08 ,  G09G2360/121 ,  G09G2360/125 ,  G09G2370/02 ,  H04L65/4023 ,  H04L67/38

Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.

公开(公告)号：EP3392764A1

公开(公告)日：2018-10-24

申请号：EP18167853.3

申请日：2018-04-17

Applicant: INTEL Corporation

Inventor： BURKE, Devan ,  LAKE, Adam T. ,  BOLES, Jeffrey S. ,  FEIT, John H. ,  VAIDYANATHAN, Karthik ,  APPU, Abhishek R. ,  RAY, Joydeep ,  MAIYURAN, Subramaniam ,  KOKER, Altug ,  VEMBU, Balaji ,  RAMADOSS, Murali ,  SURTI, Prasoonkumar ,  HOEKSTRA, Eric J. ,  LIKTOR, Gabor ,  KENNEDY, Jonathan ,  GRAJEWSKI, Slawomir ,  OULD-AHMED-VALL, Elmoustapha

IPC: G06F9/48

CPC classification number: G06T15/005 ,  G06F9/3836 ,  G06F9/4881 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：EP2936440A1

公开(公告)日：2015-10-28

申请号：EP13868697.7

申请日：2013-12-19

Applicant: Intel Corporation

Inventor： SURTI, Prasoonkumar ,  PIAZZA, Thomas A.

IPC: G06T15/00 ,  G06T1/20

CPC classification number: G06T15/503 ,  G06T11/40 ,  G06T15/005 ,  G06T2200/12 ,  G06T2210/08

Abstract: Various embodiments are generally directed to techniques for causing the storage of a color data value of a clear color to be deferred as rendered color data values are stored for samples. A device comprises a processor circuit and a storage to store instructions that cause the processor circuit to render a pixel from multiple samples taken of a three-dimensional model of an object, the pixel corresponding to a pixel sample data which comprises multiple color storage locations that are each identified by a numeric identifier, and which comprises multiple sample color indices that each correspond to a sample to point to at least one color storage location; and allocate color storage locations in an order selected to define a subset of possible combinations of binary index values among all of the sample color indices as invalid combinations. Other embodiments are described and claimed.

Abstract translation: 各种实施例通常涉及用于在为样本存储所渲染的颜色数据值时使得清除颜色的颜色数据值的存储被延迟的技术。 一种设备包括处理器电路和存储器，用于存储使得处理器电路从取自对象的三维模型的多个样本渲染像素的指令，该像素对应于包括多个颜色存储位置的像素样本数据， 每个都由数字标识符标识，并且其包括多个样本颜色索引，每个样本颜色索引对应于样本以指向至少一个颜色存储位置; 并且以所选择的顺序分配颜色存储位置，以将所有样本颜色索引中的二进制索引值的可能组合的子集定义为无效组合。 描述和要求保护其他实施例。

公开(公告)号：EP4453737A1

公开(公告)日：2024-10-30

申请号：EP22912217.1

申请日：2022-10-28

Applicant: INTEL Corporation

Inventor： SURTI, Prasoonkumar ,  KRISHNAN, Vidhya ,  APPU, Abhishek R. ,  SZERSZEN, Karol A. ,  STRIRAMASSARMA, Lakshminarayanan

IPC: G06F12/084 ,  G06F12/0888 ,  G06T1/20

公开(公告)号：EP4351233A2

公开(公告)日：2024-04-10

申请号：EP24158696.5

申请日：2018-02-23

Applicant: INTEL Corporation

Inventor： KOKER, Altug ,  APPU, Abhishek R. ,  VEERNAPU, Kiran C. ,  RAY, Joydeep ,  VEMBU, Balaji ,  SURTI, Prasoonkumar ,  SINHA, Kamal ,  HOEKSTRA, Eric J. ,  FU, Wenyin ,  KABURLASOS, Nikos ,  BOROLE, Bhushan M. ,  SCHLUESSLER, Travis T. ,  SHAH, Ankur N. ,  KENNEDY, Jonathan

IPC: H04W52/02

Abstract: An apparatus is disclosed with one or more processors including a graphics processing unit, the graphics processing unit including a graphics processing pipeline, and a memory to store data, including graphics data processed by the graphics processing pipeline, wherein the graphics processing unit is to conduct a training session with an application, the training session including a plurality of executions of the application utilizing the graphics processing pipeline, wherein the plurality of executions of the application includes executing the application under a plurality of different operating parameters, a plurality of different hardware configurations, or both, collect performance data for the application during the plurality of executions of the application, generate a performance profile for the application as processed in the graphics processing pipeline based on the collected performance data, train a neural network to configure the graphics processing pipeline based on performance profile data from the performance profile for the application, and utilize the trained neural network to configure the graphics processing pipeline to execute an instance of the application. Furthermore, a method and one or more computer-readable media are disclosed.

公开(公告)号：EP4287590A3

公开(公告)日：2024-02-14

申请号：EP23204120.2

申请日：2018-03-19

Applicant: INTEL Corporation

Inventor： LAKSHMANAN, Barath ,  HURD, Linda L. ,  ASHBAUGH, Ben J. ,  OULD-AHMED-VALL, Elmoustapha ,  MA, Liwei ,  JIN, Jingyi ,  GOTTSCHLICH, Justin E. ,  SAKTHIVEL, Chandrasekaran ,  STRICKLAND, Michael S. ,  LEWIS, Brian T. ,  KUPER, Lindsey ,  KOKER, Altug ,  APPU, Abhishek R. ,  SURTI, Prasoonkumar ,  RAY, Joydeep ,  VEMBU, Balaji ,  TUREK, Javier S. ,  FAROOQUI, Naila

IPC: H04W4/40 ,  H04L67/12 ,  B60W50/00

Abstract: One embodiment provides for a method of performing machine learning operations for an autonomous vehicle, with determining that a computational workload is to be processed by a computing device of the autonomous vehicle, determining a first latency to a remote datacenter via an autonomous vehicle network, dispatching at least a first portion of the computational workload for processing via the remote datacenter when the first latency is below a threshold associated with the computational workload, determining a second latency to an autonomous vehicle within range of wireless network device in response to a determination that the first latency is above the threshold associated with the computational workload, and dispatching at least a second portion of the computational workload in response determining that the second latency is below the threshold associated with the computational workload.

公开(公告)号：EP4296938A2

公开(公告)日：2023-12-27

申请号：EP23208333.7

申请日：2018-02-21

Applicant: INTEL Corporation

Inventor： SURTI, Prasoonkumar ,  APPU, Abhishek R. ,  RAY, Joydeep ,  MAIYURAN, Subramaniam M. ,  KOKER, Altug

IPC: G06T1/60

Abstract: An apparatus to facilitate memory tiling is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads via access to the memory and tiling logic to apply a tiling pattern to memory addresses for data stored in the memory.

公开(公告)号：EP4196961A1

公开(公告)日：2023-06-21

申请号：EP21858783.0

申请日：2021-07-20

Applicant: INTEL Corporation

Inventor： WOOP, Sven ,  DOYLE, Michael J. ,  KOTHANDARAMAN, Sreenivas ,  VAIDYANATHAN, Karthik ,  APPU, Abhishek R. ,  BENTHIN, Carsten ,  SURTI, Prasoonkumar ,  GRÜEN, Holger ,  JUNKINS, Stephen ,  LAKE, Adam ,  ALFIERI, Bret G. ,  LIKTOR, Gabor ,  BARCZAK, Joshua ,  LEE, Won-Jong

IPC: G06T15/50 ,  G06T15/60

公开(公告)号：EP3944077A1

公开(公告)日：2022-01-26

申请号：EP21197376.3

申请日：2019-06-28

Applicant: INTEL Corporation

Inventor： BAUM, Dan ,  ZOHAR, Ronen ,  MISHRA, Asit ,  SURTI, Prasoonkumar ,  ELMOUSTAPHA, Ould-Ahmed-Vall ,  HUGHES, Christopher ,  HEINECKE, Alexander

IPC: G06F9/30

Abstract: Disclosed embodiments relate to apparatuses, systems, and methods for performing sort indexing and/or permutation using an index. An exemplary apparatus or processor comprises decode circuitry to decode an instruction, the instruction to include a first field to identify a location of a source vector, a second field to identify a location of a destination vector, and an opcode to indicate to execution circuitry to execute the decoded instruction to sort values of the source vector and store a result of the sort in the destination vector by generating, per each element of the source vector, an index value, and permuting the values of the elements of the source vector into the destination vector based upon the index values for the element, and execution circuitry to execute the decoded instruction as indicated by the opcode.