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公开(公告)号：US11209892B2
公开(公告)日：2021-12-28
申请号：US16992701
申请日：2020-08-13
Applicant: Intel Corporation
Inventor： Mohammed Tameem , Altug Koker , Kiran C. Veernapu , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Travis T. Schluessler , Jonathan Kennedy
IPC: G06F1/3234 , G06F13/16 , G06F13/40 , G06F1/3296 , G06F1/324 , G06F1/3206 , G06F1/3287
Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client.
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公开(公告)号：US20210349715A1
公开(公告)日：2021-11-11
申请号：US17319056
申请日：2021-05-12
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
Abstract: In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20210304485A1
公开(公告)日：2021-09-30
申请号：US17180188
申请日：2021-02-19
Applicant: Intel Corporation
Inventor： Nikos Kaburlasos , Joydeep Ray , John H. Feit , Travis T. Schluessler , Jacek Kwiatkowski , Philip R. Laws
IPC: G06T15/00 , H04N13/344 , H04N13/398
Abstract: An embodiment of a parallel processor apparatus may include a sample pattern selector to select a sample pattern for a pixel, and a sample pattern subset selector communicatively coupled to the sample pattern selector to select a first subset of the sample pattern for the pixel corresponding to a left eye display frame and to select a second subset of the sample pattern for the pixel corresponding to a right eye display frame, wherein the second subset is different from the first subset. Other embodiments are disclosed and claimed.
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公开(公告)号：US11106262B2
公开(公告)日：2021-08-31
申请号：US16421647
申请日：2019-05-24
Applicant: Intel Corporation
Inventor： Travis T. Schluessler , Russell J. Fenger
IPC: G06F1/32 , G06F1/3206 , G06F1/20 , G06F1/3287 , G06F1/329 , G06F9/50 , G06F1/3203 , G06F1/3234
Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.
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95.发明授权公开(公告)号：US10991075B2
公开(公告)日：2021-04-27
申请号：US16125121
申请日：2018-09-07
Applicant: Intel Corporation
Inventor： Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Abhishek R. Appu , Balaji Vembu , Prasoonkumar Surti
Abstract: Systems, apparatuses and methods may provide away to blend two or more of the scene surfaces based on the focus area and an offload threshold. More particularly, systems, apparatuses and methods may provide a way to blend, by a display engine, two or more of the focus area scene surfaces and blended non-focus area scene surfaces. The systems, apparatuses and methods may include a graphics engine to render the focus area surfaces at a higher sample rate than the non-focus area scene surfaces.
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Patent Agency Ranking
公开(公告)号：US20210035257A1
公开(公告)日：2021-02-04
申请号：US16985329
申请日：2020-08-05
Applicant: Intel Corporation
Inventor： Saurabh Sharma , Abhishek Venkatesh , Travis T. Schluessler , Prasoonkumar Surti , Altug Koker , Aravindh V. Anantaraman , Pattabhiraman P. K. , Abhishek R. Appu , Joydeep Ray , Kamal Sinha , Vasanth Ranganathan , Bhushan M. Borole , Wenyin Fu , Eric J. Hoekstra , Linda L. Hurd
Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
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公开(公告)号：US10896657B2
公开(公告)日：2021-01-19
申请号：US15488561
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Louis Feng , Altug Koker , Tomasz Janczak , Andrew T. Lauritzen , David M. Cimini , Nikos Kaburlasos , Joydeep Ray , John H. Feit , Travis T. Schluessler , Jacek Kwiatkowski , Philip R. Laws , Devan Burke , Elmoustapha Ould-Ahmed-Vall , Abhishek R. Appu
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.
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公开(公告)号：US10891774B2
公开(公告)日：2021-01-12
申请号：US15692973
申请日：2017-08-31
Applicant: Intel Corporation
Inventor： Travis T. Schluessler , Michael Apodaca , Peng Guo , William B. Davidson , Guei-Yuan Lueh
Abstract: An apparatus and method for collecting and using profile data during graphics processing. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics commands responsive to execution of an application; and profile storage to store graphics execution profile data associated with one or more graphics workloads; and a profile manager to read the profile data upon detecting one of the graphics workloads during execution of the application and to configure the graphics processor in accordance with the profile data.
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公开(公告)号：US10761589B2
公开(公告)日：2020-09-01
申请号：US15493243
申请日：2017-04-21
Applicant: Intel Corporation
Inventor： Mohammed Tameem , Altug Koker , Kiran C. Veernapu , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Travis T. Schluessler , Jonathan Kennedy
IPC: G06F1/32 , G06F1/3234 , G06F13/16 , G06F13/40 , G06F1/3296 , G06F1/324 , G06F1/3206 , G06F1/3287
Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client.
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100.发明授权公开(公告)号：US10719902B2
公开(公告)日：2020-07-21
申请号：US15488842
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Travis T. Schluessler , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Altug Koker , Jacek Kwiatkowski , Ingo Wald , Jefferson Amstutz , Johannes Guenther , Gabor Liktor , Elmoustapha Ould-Ahmed-Vall
Abstract: Systems, apparatuses, and methods may provide for technology to process graphical data, and to modify a runtime environment in a parallel computing platform for a graphic environment.
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