公开(公告)号：US10929947B2

公开(公告)日：2021-02-23

申请号：US16572161

申请日：2019-09-16

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Ankur N. Shah ,  Abhishek R. Appu ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall ,  Atsuo Kuwahara ,  Travis T. Schluessler ,  Linda L. Hurd ,  Josh B. Mastronarde ,  Vasanth Ranganathan

IPC: G06T1/20 ,  G06F9/30 ,  G06T15/00 ,  G06F9/38

Abstract: An embodiment of a graphics apparatus may include a context engine to determine contextual information, a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information, and a configuration engine communicatively coupled to the recommendation engine to adjust a configuration of a graphics operation based on the recommendation. Other embodiments are disclosed and claimed.

公开(公告)号：US10909039B2

公开(公告)日：2021-02-02

申请号：US16355015

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Vikranth Vemulapalli ,  Lakshminarayanan Striramassarma ,  Mike MacPherson ,  Aravindh Anantaraman ,  Ben Ashbaugh ,  Murali Ramadoss ,  William B. Sadler ,  Jonathan Pearce ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter, Jr. ,  Prasoonkumar Surti ,  Nicolas Galoppo von Borries ,  Joydeep Ray ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Altug Koker ,  Sungye Kim ,  Subramaniam Maiyuran ,  Valentin Andrei

IPC: G09G5/36 ,  G06F12/0862 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

公开(公告)号：US20200341942A1

公开(公告)日：2020-10-29

申请号：US16847781

申请日：2020-04-14

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  James A. Valerio ,  Altug Koker ,  Abhishek R. Appu ,  Vasanth Ranganathan

IPC: G06F15/80 ,  G06T1/20

Abstract: A shared local memory data crossbar may be implemented in multiple stages. With this approach, the number of multiplexer cells can be reduced by fifty percent (50%) or more in some embodiments.

公开(公告)号：US20200293450A1

公开(公告)日：2020-09-17

申请号：US16355015

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Vikranth Vemulapalli ,  Lakshminarayanan Striramassarma ,  Mike MacPherson ,  Aravindh Anantaraman ,  Ben Ashbaugh ,  Murali Ramadoss ,  William B. Sadler ,  Jonathan Pearce ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter, JR. ,  Prasoonkumar Surti ,  Nicolas Galoppo von Borries ,  Joydeep Ray ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Altug Koker ,  Sungye Kim ,  Subramaniam Maiyuran ,  Valentin Andrei

IPC: G06F12/0862 ,  G06T1/60 ,  G06T1/20

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

公开(公告)号：US10776897B1

公开(公告)日：2020-09-15

申请号：US16297129

申请日：2019-03-08

Applicant: Intel Corporation

Inventor： James Valerio ,  Vasanth Ranganathan ,  Joydeep Ray ,  Abhishek R. Appu ,  Ben J. Ashbaugh ,  Brandon Fliflet ,  Jeffery S. Boles ,  Srinivasan Embar Raghukrishnan ,  Rahul Kulkarni

IPC: G06T1/20 ,  G06T1/60

Abstract: Embodiments described herein provide an apparatus comprising a processor to configure a plurality of contexts of a command engine to execute a graphics workload comprising a plurality of walkers, allocate, from a pool of execution units of a graphics processor, a subset of execution units to each walker in the plurality of walkers based at least in part on the predetermined number of walkers configured for the context, for each context in the plurality of contexts, dispatch one or more walkers of the plurality of walkers to the execution units, and upon dispatch of the one or more walkers of the plurality of walkers, write an opcode to a computer-readable memory indicating that the dispatch of the walker is complete, wherein the opcode comprises dependency data for the one or more walkers of the plurality of walkers. Other embodiments may be described and claimed.

公开(公告)号：US10748238B2

公开(公告)日：2020-08-18

申请号：US16279270

申请日：2019-02-19

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Abhishek Venkatesh ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  Altug Koker ,  Aravindh V. Anantaraman ,  Pattabhiraman P. K. ,  Abhishek R. Appu ,  Joydeep Ray ,  Kamal Sinha ,  Vasanth Ranganathan ,  Bhushan M. Borole ,  Wenyin Fu ,  Eric J. Hoekstra ,  Linda L. Hurd

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

公开(公告)号：US10713750B2

公开(公告)日：2020-07-14

申请号：US15477018

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Abhishek R. Appu ,  Vasanth Ranganathan

IPC: G06T1/60 ,  G06F12/127 ,  G06F12/0815 ,  G06F12/123

Abstract: An apparatus to facilitate cache replacement is disclosed. The apparatus includes a cache memory and cache replacement logic to manage data in the cache memory. The cache replacement logic includes tracking logic to track addresses accessed at the cache memory and replacement control logic to monitor the tracking logic and apply a replacement policy based on information received from the tracking logic.

公开(公告)号：US20200160564A1

公开(公告)日：2020-05-21

申请号：US16659907

申请日：2019-10-22

Applicant: Intel Corporation

Inventor： Altug Koker ,  Vasanth Ranganathan ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T9/00 ,  G06T1/20

Abstract: A mechanism is described for facilitating fabric-based compression and/or decompression of data at computing devices. A method of embodiments, as described herein, includes compressing contents of a data stream traveling through an internal fabric between a source component and a destination component, wherein the contents are compressed on the internal fabric.

公开(公告)号：US20200111454A1

公开(公告)日：2020-04-09

申请号：US16599175

申请日：2019-10-11

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan K. Bhiravabhatla ,  Arthur D. Hunter, JR. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

IPC: G09G5/36 ,  G09G5/00 ,  G06F9/46 ,  G06F12/0875

Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

公开(公告)号：US20190317899A1

公开(公告)日：2019-10-17

申请号：US16394829

申请日：2019-04-25

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  James A. Valerio ,  Abhishek R. Appu ,  Vasanth Ranganathan

IPC: G06F12/0842 ,  G06F12/0831 ,  G06F12/0811 ,  G06T1/60

Abstract: A mechanism is described for facilitating independent and separate entity-based graphics cache at computing devices. A method of embodiments, as described herein, includes facilitate hosting of a plurality of cache at a plurality of entities associated with a graphics processor, wherein each entity hosts at least one cache, and wherein an entity includes a dual sub-slice (DSS) or a streaming multiprocessor (SM).