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公开(公告)号:US20180284871A1
公开(公告)日:2018-10-04
申请号:US15477006
申请日:2017-04-01
Applicant: Intel Corporation
Inventor: Prasoonkumar Surti , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Joydeep Ray , Elmoustapha Ould-Ahmed-Vall , Deepak S. Vembar , Abhishek R. Appu , Ankur N. Shah
CPC classification number: G06F1/3287 , G06F1/3243
Abstract: Methods and apparatus relating to techniques for shutting down one or more GPU (Graphics Processing Unit) components in response to unchanged scene detection are described. In one embodiment, one or more components of a processor enter a low power consumption state in response to a determination that a scene to be displayed is static. The static scene is displayed on a display device (e.g., based on information to be retrieved from memory) for as long as no change to the static scene is detected. Other embodiments are also disclosed and claimed.
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公开(公告)号:US09164931B2
公开(公告)日:2015-10-20
申请号:US13631921
申请日:2012-09-29
Applicant: Intel Corporation
Inventor: Linda L. Hurd , Wenyin Fu
CPC classification number: G06F13/14 , G06F13/4072 , G06T1/00 , Y02D10/14 , Y02D10/151
Abstract: Methods and apparatus relating to clamping or reducing of dynamic capacitance for graphics logic are described. In one embodiment, utilization values for a plurality of subsystems of a graphics logic are determined and a first capacitance value is in turn determined based on (e.g., a sum of products of) the determined utilization values (e.g., and one or more capacitance weight values). A second capacitance value (e.g., corresponding to a maximum dynamic capacitance or Cdyn_max corresponding to the graphics logic) is modified based on (e.g., a comparison of the first capacitance value and a (e.g., threshold) capacitance value. Other embodiments are also disclosed and claimed.
Abstract translation: 描述了与图形逻辑的动态电容的钳位或减小相关的方法和装置。 在一个实施例中,确定图形逻辑的多个子系统的利用率值,并且依次(例如,所确定的利用值的乘积之和)(例如,和一个或多个电容权重)来确定第一电容值 值)。 基于(例如,第一电容值和(例如,阈值)电容值的比较)来修改第二电容值(例如,对应于对应于图形逻辑的最大动态电容或Cdyn_max),还公开了其他实施例 并声称。
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