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公开(公告)号：US10936214B2
公开(公告)日：2021-03-02
申请号：US16441338
申请日：2019-06-14
Applicant: Intel Corporation
Inventor： Travis T. Schluessler , Prasoonkumar Surti , Aravindh V. Anantaraman , Abhishek R. Appu , Joydeep Ray , Altug Koker , Balaji Vembu
IPC: G06F3/06 , G06F1/3234 , G06F1/3225 , G11C11/406 , G11C11/4074
Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a memory comprising one or more physical memory chips, and a processor to implement a working set monitor to monitor a working set resident in the one or more physical memory chips. The working set monitor is to adjust a number of the physical memory chips that are powered on based on a size of the working set.
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公开(公告)号：US10929749B2
公开(公告)日：2021-02-23
申请号：US15494948
申请日：2017-04-24
Applicant: Intel Corporation
Inventor： Narayan Srinivasa , Joydeep Ray , Nicolas C. Galoppo Von Borries , Ben Ashbaugh , Prasoonkumar Surti , Feng Chen , Barath Lakshmanan , Elmoustapha Ould-Ahmed-Vall , Liwei Ma , Linda L. Hurd , Abhishek R. Appu , John C. Weast , Sara S. Baghsorkhi , Justin E. Gottschlich , Chandrasekaran Sakthivel , Farshad Akhbari , Dukhwan Kim , Altug Koker , Nadathur Rajagopalan Satish
Abstract: An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.
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公开(公告)号：US20210050070A1
公开(公告)日：2021-02-18
申请号：US17006192
申请日：2020-08-28
Applicant: Intel Corporation
Inventor： Altug Koker , Travis T. Schluessler , Ankur N. Shah , Abhishek R. Appu , Joydeep Ray , Jonathan Kennedy
Abstract: Systems, apparatuses and methods may provide for technology that identifies a redundant portion of a packaged on-die memory and detects, during a field test of the packaged on-die memory, one or more failed cells in the packaged on-die memory. Additionally, one or more memory cells in the redundant portion may be substituted for the one or more failed memory cells.
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公开(公告)号：US20210042983A1
公开(公告)日：2021-02-11
申请号：US17069406
申请日：2020-10-13
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Prasoonkumar Surti , Joydeep Ray , Michael J. Norris
Abstract: One embodiment provides for a data processing system comprising a memory module to store a multisample render target, the multisample render target to store multiple sample locations for each pixel in a set of pixels and a general-purpose graphics processor including a hardware graphics rendering pipeline to generate pixel color data to be output to the multisample render target, a multisample antialiasing compressor to request allocation of one or more planes to store color data for a set of sample locations of a pixel in the set of pixels, and a memory allocator to allocate memory to store color data associated with the multisample render target. The memory allocator can merge a memory allocation for multiple pixels having a sample associated with a same color value.
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公开(公告)号：US20210035259A1
公开(公告)日：2021-02-04
申请号：US16930935
申请日：2020-07-16
Applicant: Intel Corporation
Inventor： Vasanth Ranganathan , Saikat Mandal , Karol A. Szerszen , Saurabh Sharma , Vamsee Vardhan Chivukula , Abhishek R. Appu , Joydeep Ray , Prasoonkumar Surti , Altug Koker
IPC: G06T1/60 , G06F12/0875 , G06T1/20
Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.
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Patent Agency Ranking
公开(公告)号：US20210034135A1
公开(公告)日：2021-02-04
申请号：US16992701
申请日：2020-08-13
Applicant: Intel Corporation
Inventor： Mohammed Tameem , Altug Koker , Kiran C. Veernapu , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Travis T. Schluessler , Jonathan Kennedy
IPC: G06F1/3234 , G06F13/16 , G06F13/40 , G06F1/3296 , G06F1/324 , G06F1/3206 , G06F1/3287
Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client.
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公开(公告)号：US10909037B2
公开(公告)日：2021-02-02
申请号：US15493404
申请日：2017-04-21
Applicant: Intel Corporation
Inventor： Joydeep Ray , Abhishek R. Appu , Altug Koker , James A. Valerio , Prasoonkumar Surti
IPC: G09G5/36 , G06F12/0844 , G06T1/60
Abstract: A mechanism is described for facilitating memory address compression at computing devices. A method of embodiments, as described herein, includes coalescing slot addresses across multiple messages received from an execution unit, where the slot addresses are coalesced in groups based on memory cacheline addresses such that each of a set of slot addresses in a group have a memory cacheline address in common between them. The method may further include outputting the memory cacheline addresses.
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公开(公告)号：US10908905B2
公开(公告)日：2021-02-02
申请号：US16599239
申请日：2019-10-11
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , Balaji Vembu , Abhishek R. Appu , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to determine a first number of threads to be scheduled for each context of a plurality of contexts in a multi-context processing system, allocate a second number of streaming multiprocessors (SMs) to the respective plurality of contexts, and dispatch threads from the plurality of contexts only to the streaming multiprocessor(s) allocated to the respective plurality of contexts. Other embodiments are also disclosed and claimed.
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公开(公告)号：US10904535B2
公开(公告)日：2021-01-26
申请号：US15495531
申请日：2017-04-24
Applicant: Intel Corporation
Inventor： Jong Dae Oh , Abhishek R. Appu , Stanley J. Baran , Sang-Hee Lee , Atthar H. Mohammed , Hiu-Fai R. Chan , Joydeep Ray
IPC: H04N7/12 , H04N19/156 , H04N7/01 , H04N19/132 , H04N19/172 , G06T1/20
Abstract: Systems and methods may provide for occlusion detection in frame rate conversion. Detecting the occlusion allows frame rate conversion to be more accurately performed. In some embodiments, one or more stereoscopic depth cameras may be used to determine the depth of a moving object to more accurately determine the occlusion. In some embodiments, the compression ratio may be adjusted to balance the frame rate and power to help ensure compliance with a power budget. In at least some embodiments, the motion of a camera may be passed from a 3D render pipe to an encoder to avoid motion calculation and thereby saving power.
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公开(公告)号：US10902546B2
公开(公告)日：2021-01-26
申请号：US15493324
申请日：2017-04-21
Applicant: Intel Corporation
Inventor： Kiran C. Veernapu , Abhishek R. Appu , Prasoonkumar Surti , Arijit Mukhopadhyay , Altug Koker , Joydeep Ray
Abstract: A mechanism is described for facilitating selective skipping of compression cycles in computing devices. A method of embodiments, as described herein, includes facilitating determining a first current output relating to compression of a current set of data to be same as a previous output from compression of a previous set of data, and turning off a compression engine to skip compression of the current set of data.
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