公开(公告)号：US09748371B2

公开(公告)日：2017-08-29

申请号：US15120496

申请日：2014-03-21

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Sansaptak Dasgupta ,  Han Wui Then ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/786 ,  H01L29/24 ,  H01L21/02 ,  H01L21/8256 ,  H01L27/12 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7782 ,  H01L21/02422 ,  H01L21/02568 ,  H01L21/8256 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/0843 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78681

Abstract: Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a first barrier formed of a first transition metal dichalcogenide (TMD) material, a transistor channel formed of a second TMD material, and a second barrier formed of a third TMD material. The first barrier may be disposed between the transistor channel and the flexible substrate, the transistor channel may be disposed between the second barrier and the first barrier, and a bandgap of the transistor channel may be less than a bandgap of the first barrier and less than a bandgap of the second barrier. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US20170221999A1

公开(公告)日：2017-08-03

申请号：US15492785

申请日：2017-04-20

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Robert S. Chau

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/66 ,  H01L21/308 ,  H01L29/04 ,  H01L29/06

Abstract: An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.

公开(公告)号：US09673045B2

公开(公告)日：2017-06-06

申请号：US14908112

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Robert S. Chau

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/8258 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L21/0243 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/8258 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7787

Abstract: An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.

公开(公告)号：US09666708B2

公开(公告)日：2017-05-30

申请号：US15120705

申请日：2014-03-26

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Benjamin Chu-Kung ,  Sansaptak Dasgupta ,  Robert S. Chau ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L21/8252 ,  H01L27/06 ,  H01L21/02 ,  H01L21/033 ,  H01L29/08 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/0332 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: Techniques related to III-N transistors having enhanced breakdown voltage, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a hardmask having an opening over a substrate, a source, a drain, and a channel between the source and drain, and a portion of the source or the drain disposed over the opening of the hardmask.

公开(公告)号：US09590069B2

公开(公告)日：2017-03-07

申请号：US14752365

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Niti Goel ,  Sanaz Kabehie Gardner ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L29/66 ,  H01L21/338 ,  H01L29/205 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L21/223 ,  H01L29/778 ,  H01L29/08 ,  H01L29/423 ,  H01L29/20 ,  H01L29/207

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

Abstract translation: 实施例包括高电子迁移率晶体管（HEMT）。 在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。 在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。 在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。

公开(公告)号：US20160365341A1

公开(公告)日：2016-12-15

申请号：US14738799

申请日：2015-06-12

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak Dasgupta ,  Gerhard Schrom ,  Valluri R. Rao ,  Robert S. Chau

IPC: H01L27/06 ,  H01L29/04 ,  H01L29/20 ,  H01L29/10 ,  H01L29/205 ,  H01L29/94 ,  H01L29/778

CPC classification number: H01L27/0629 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66181 ,  H01L29/7787 ,  H01L29/94 ,  H01L29/945

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

Abstract translation: 集成了至少一个具有高击穿电压（BV）的III-N MOS电容器的III-N高压MOS电容器和片上系统（SoC）解决方案，以实现高压和/或高功率电路。 可以实现超过4V的击穿电压，避免了RFIC和/或PMIC中的串联耦合电容的任何需要。 在实施例中，包括其中在低于0V的阈值电压下形成二维电子气（2DEG）的GaN层的耗尽型III-N电容器与IV族晶体管架构单片集成，例如平面和非平面硅CMOS晶体管技术 。 在实施例中，蚀刻硅衬底以提供形成GaN层和III-N势垒层的（111）外延生长表面。 在实施例中，沉积高K电介质层，并且电容器端子触点被制成2DEG并且在电介质层上。

公开(公告)号：US11942378B2

公开(公告)日：2024-03-26

申请号：US17675961

申请日：2022-02-18

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/778 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/04 ,  H01L29/267 ,  H01L29/66 ,  H01L29/73

CPC classification number: H01L21/8252 ,  H01L27/0605 ,  H01L29/045 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/73 ,  H01L29/778

Abstract: Techniques related to III-N transistors having improved performance, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include first and second crystalline III-N material layers separated by an intervening layer other than a III-N material such that the first crystalline III-N material layer has a first crystal orientation that is inverted with respect to a second crystal orientation of the second crystalline III-N material layer.

公开(公告)号：US11784121B2

公开(公告)日：2023-10-10

申请号：US17700198

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Nicholas James Harold McKubre ,  Richard Farrington Vreeland ,  Sansaptak Dasgupta

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/525 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53209 ,  H01L21/76852 ,  H01L23/5222 ,  H01L23/5256 ,  H01L28/10

Abstract: Disclosed herein are integrated circuit (IC) components with dummy structures, as well as related methods and devices. For example, in some embodiments, an IC component may include a dummy structure in a metallization stack. The dummy structure may include a dummy material having a higher Young's modulus than an interlayer dielectric of the metallization stack.

公开(公告)号：US11728346B2

公开(公告)日：2023-08-15

申请号：US17501914

申请日：2021-10-14

Applicant: INTEL CORPORATION

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/66795 ,  H01L29/7851

Abstract: A device including a III-N material is described. In an example, the device has a terminal structure with a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer including a III-N material in the terminal structure. A gate electrode is disposed above and on a portion of the polarization charge inducing layer. A source structure is on the polarization charge inducing layer and on sidewalls of the first plurality of fins. A drain structure is on the polarization charge inducing layer and on sidewalls of the second plurality of fins. The device further includes a source structure and a drain structure on opposite sides of the gate electrode and a source contact on the source structure and a drain contact on the drain structure.

公开(公告)号：US11715799B2

公开(公告)日：2023-08-01

申请号：US17526562

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Han Wui Then

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L29/7851 ,  H01L21/8258 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/66795

Abstract: Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping are disclosed. An example integrated circuit includes a group III-nitride substrate and a fin of silicon formed on the group III-nitride substrate. The integrated circuit further includes a first transistor formed on the fin of silicon and a second transistor formed on the group III-nitride substrate.