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公开(公告)号：JPH0467156B2
公开(公告)日：1992-10-27
申请号：JP11800083
申请日：1983-06-28
Applicant: SONY CORP
Inventor： HAMADA OSAMU , KATSUMATA YASUSHI
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公开(公告)号：JPH01296707A
公开(公告)日：1989-11-30
申请号：JP12660288
申请日：1988-05-24
Applicant: SONY CORP
Inventor： SHIRAKO YUKIO , HAMADA OSAMU
Abstract: PURPOSE:To output data of plural systems in an optional timing of one data output period by using a timing matching register so as to match the timing of the output data of plural systems. CONSTITUTION:An output data of a selector 25 is as shown in figure A and an output DA', DB' have a period of 1/Fs. A data storage clock corresponding to the end of the output data DA' is supplied to a register 26 as shown in figure B and the content of the register 26 is as shown in figure C. Moreover, the data storage clock corresponding to the end of the output data DB' is supplied to registers 27A, 27B as shown in figure D, the content of the registers 27A, 27B is as shown in figures E, F respectively to match the timing of the output data DA', DB'. Thus, the output data of plural systems is outputted in an optional timing of one data output period and the circuit copes with any form of output excellently.
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公开(公告)号：JPS62267798A
公开(公告)日：1987-11-20
申请号：JP11157086
申请日：1986-05-15
Applicant: SONY CORP
Inventor： HAMADA OSAMU , YAMAMORI YASUSHI
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公开(公告)号：JPS62266596A
公开(公告)日：1987-11-19
申请号：JP10999386
申请日：1986-05-14
Applicant: SONY CORP
Inventor： HAMADA OSAMU , IMURA SHIGERU
IPC: G10H7/00
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公开(公告)号：JPS62105518A
公开(公告)日：1987-05-16
申请号：JP24582785
申请日：1985-11-01
Applicant: SONY CORP
Inventor： HAMADA OSAMU
Abstract: PURPOSE:To perform a double-precision arithmetic with the coefficient of single precision and to perform a fast arithmetic with a small-scale circuit constitution by dividing a multiplier coefficient sequence corresponding to the impulse response of a filter into a large-coefficient and small-coefficient parts, and performing the double-precision arithmetic for only the large-coefficient part by partial product arithmetic. CONSTITUTION:The clock of a multiplier between the number N of filters and the frequency of a sample sequence is counted by the counter 6 of a digital filter and applied as an address to a ROM 2, and a series of coefficients is read out and applied to a multiplier 3. Further, a counter 8 counts the clock of frequency fs and applies it to an adder 7 together with the address of the ROM 2, and a data sequence corresponding to the processing of each delay stage is readout with its output and applied to the multiplier 3. The multiplication result of this multiplier 3 is accumulated by accumulator 5 through an adder 4. A part of the accumulation result is fed back to an adder 4 through a shifter 9 and the sum of products is calculated by convolution, etc., to simplifying the circuit constitution, thereby performing fast arithmetic.
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Patent Agency Ranking
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公开(公告)号：JPS61246961A
公开(公告)日：1986-11-04
申请号：JP29536085
申请日：1985-12-25
Applicant: SONY CORP
Inventor： DOI TOSHITADA , IGA AKIRA , HAMADA OSAMU
IPC: G11B27/029 , G11B20/10 , G11B27/032 , G11B27/036
Abstract: PURPOSE:To enable after-recording by converting in series PCM signals of plural channels in which other PCM signals are inserted into an optional channel, supplying them to another magnetic head and recording them again. CONSTITUTION:When, for instance, channels 1...3, 5...8 are recorded, and a channel 4 is empty, after-sound recording of the channel 4 is made. When a connecting switch 5d is turned on, a changeover switch 12d supplies outputs of a series-parallel circuit to the input terminal 13d of a signal arranging circuit 13. Thus, when connection of circuits is made by a group of switches, signals of channels 1...3, 5...8 are read by a magnetic head A or C for reproducing, and then, reproduced channels 1...3, 5...8 are recorded by magnetic heads for recording B and D. At this time, after-sound recording can be made by making recording on the empty channel 4.
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公开(公告)号：JPS6172335A
公开(公告)日：1986-04-14
申请号：JP19329384
申请日：1984-09-14
Applicant: Sony Corp
Inventor： HAMADA OSAMU
CPC classification number: G06F7/556
Abstract: PURPOSE:To attain a calculation method of simple constitution with a small number of conversion tables by performing the logarithm conversion after executing the sequential algorithm by the program of a digital signal processor. CONSTITUTION:When the logarithm conversion (Y=logaX) is carried out, a window is provided to a prescribed bit of the Y information consisting of plural bits. Then the data on the X information is supplied to the 1st register and the initial value of the X information is supplied to the 2nd register. A coeffi cient pointer related to the (a) information is initialized. The coefficient corre sponding to said coefficient point and the multiplied value of the holding value of the X information are compared with data. If the multiplied value is larger than the data, this multiplied value is supplied to the 2nd register in place of the holding value of the X information. Then a specific bit is set up at a prescribed bit of the Y information. While the window is shifted and at the same time the coefficient is changed for repetition of said comparison in case the multiplied value is smaller than the data.
Abstract translation: 目的：通过数字信号处理器的程序执行顺序算法后，通过执行对数转换，获得具有少量转换表的简单结构的计算方法。 构成：当进行对数转换（Y = logaX）时，向由多个位组成的Y信息的指定位提供一个窗口。 然后将X信息上的数据提供给第一个寄存器，并将X信息的初始值提供给第二个寄存器。 与（a）信息相关的系统指针被初始化。 将与所述系数点相对应的系数和X信息的保持值的相乘值与数据进行比较。 如果相乘值大于数据，则将该乘法值提供给第二寄存器，而不是X信息的保持值。 然后在Y信息的规定位设置特定位。 当窗口被移位并且同时改变系数以重复所述比较，在倍数值小于数据的情况下。
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公开(公告)号：JPS6157127A
公开(公告)日：1986-03-24
申请号：JP17883884
申请日：1984-08-28
Applicant: Sony Corp
Inventor： HAMADA OSAMU
Abstract: PURPOSE: To attain smooth switching of signal conversion by using the 1st and 2nd digital signal processors to apply measurement correction in real time to a DC offset and gain error of plural D/A converters and A/D converters.
CONSTITUTION: An analog input signal is fed to A/D converters 4, 5 via an LPF 2 and a sample and hold circuit 3 to convert it into a digital signal. The converter 4 is used for a small sound with high sensitivity and the converter 5 is used for a large sound with low sensitivity. The digital signal of the converters 4, 5 is fetched to a digital signal processor 20 at the same time, where the variance in the DC offset and gain is corrected and the result is fed to a tape recorder 8. The signal from the recorder 8 is fed to a digital signal processor 21, where the variance in the DC offset and gain is corrected based on a 1-bit output from the comparator provided at the output of the D/A converters 9, 10 and the result is fed to D/A converters 9, 10 and a switch 12 is switched automatically and momentarily to output a signal converted into an analog signal via an LPF 13.
COPYRIGHT: (C)1986,JPO&JapioAbstract translation: 目的：通过使用第1和第2数字信号处理器实时实时测量校正到多个D / A转换器和A / D转换器的直流偏移和增益误差，实现信号转换的平滑切换。 构成：模拟输入信号通过LPF 2和采样保持电路3馈送到A / D转换器4,5，以将其转换为数字信号。 转换器4用于具有高灵敏度的小声音，并且转换器5用于具有低灵敏度的大声音。 转换器4,5的数字信号同时被提取到数字信号处理器20，其中DC偏移和增益的变化被校正，并将结果馈送到磁带记录器8.来自记录器8的信号 馈送到数字信号处理器21，其中基于来自D / A转换器9,10的输出端的比较器的1位输出校正DC偏移和增益的变化，并将结果馈送到D / A转换器9,10和开关12被自动切换，以经由LPF 13输出转换成模拟信号的信号。
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公开(公告)号：JPS60180319A
公开(公告)日：1985-09-14
申请号：JP3638584
申请日：1984-02-28
Applicant: SONY CORP
Inventor： HAMADA OSAMU , KITAZATO NAOHISA
Abstract: PURPOSE:To prevent a click noise at change of adjustment from being caused by comparing a setting value before set change and a setting value after set change at the set change of a setting means and adding or subtracting a step by each set amount corresponding to one or an optional fraction step of a set change step of the characteristic provided to a coefficient table to the set value before the set change. CONSTITUTION:A random access memory (RAM) 11 for storage delay of data is connected to a digital signal processing unit (DSP) 10. A memory control unit (MCU) 12 controlling the RAM11 is provided. A signal representing the state from the DSP10 and a control signal from a host CPU13 are applied to the MCU12 and an address of the RAM11 is controlled according to the signals. Moreover, a signal representing the adjusting position from variable resistors 141, 142...148 being adjusting means of an equalizer characteristic is applied the CPU13, the coefficient required for the characteristic is extracted by retrieving a read-only memory being the coefficient table and applied to the DSP10 and the MCU12.
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