公开(公告)号：WO1985002048A1

公开(公告)日：1985-05-09

申请号：PCT/US1984001783

申请日：1984-11-02

Applicant: BURROUGHS CORPORATION

Inventor： BURROUGHS CORPORATION ,  BASS, Leland, Jay ,  SHAH, Ashwin, Vasanji ,  WICKWIRE, Ralph, Owen

IPC: G09G01/02

CPC classification number: G09G5/14 ,  G09G5/06

Abstract: A system for electronically displaying multiple images on a CRT screen (16) such that some of the images are more prominent than others comprises: a control memory (14) for storing control signals which partition the screen into an array of blocks, define multiple prioritized viewports by indicating which blocks are included in each viewport, and correlate respective image pixels to each viewport; a circuit (15) for determining, from the control signals, the identity of the highest priority viewport to include a particular block; a plurality of color map memories (71) each of which contains a plurality of color signals; a correlator (77) for addressing a particular color map memory of said plurality based on the identity of the highest priority viewport; and a circuit for transferring respective color signals from the addressed color map memory to the screen based on the image pixels in the block of the highest priority viewport.

公开(公告)号：WO1985000461A1

公开(公告)日：1985-01-31

申请号：PCT/US1984001079

申请日：1984-07-11

Applicant: BURROUGHS CORPORATION

Inventor： BURROUGHS CORPORATION ,  PHELPS, Andrew, E.

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A new and improved content addressable memory cell (m), which cell (m) stores data supplied on a load data input terminal (50-m) thereof. The disclosed memory cell (m) is adapted for comparing data supplied on a compare data input terminal (10-m) thereof with data stored in the cell (m), and for supplying an output signal on a match data output terminal (54) when the compare data is the same as the data stored in the cell (m). A latch circuit (66, 68) is employed as the storage element of the cell (m). First (Q10, Q6) and second (Q12, Q8) means are each coupled between a reference potential and the match data output terminal (54), which means (Q10, Q6), and (Q12, Q8) are operative in response to the state of the latch circuit (66, 68) and the compare data supplied on the compare data input terminal (10-m).

公开(公告)号：WO1985000450A1

公开(公告)日：1985-01-31

申请号：PCT/US1984000996

申请日：1984-06-27

Applicant: BURROUGHS CORPORATION

Inventor： BURROUGHS CORPORATION ,  SHETH, Jayesh, V.

IPC: G06F03/00

CPC classification number: G06F3/0601 ,  G06F13/124 ,  G06F2003/0698

Abstract: A peripheral-controller (20t) is used to manage data transfers between magnetic tape peripheral units (50) and a main host computer (10), as depicted in (Fig. 1). A program sequencer in the peripheral-controller can initiate an automatic read-write selection logic and control unit (Fig. 2) to operate in the "automatic write" mode whereby an automatic write-logic unit (Fig. 9) will transfer data out of a buffer memory (RAM 22) in the peripheral-controller and into a magnetic tape control unit (50tc) on a continuous basis without further instructions being required from the program sequencer.

公开(公告)号：WO1985000449A1

公开(公告)日：1985-01-31

申请号：PCT/US1984000991

申请日：1984-06-27

Applicant: BURROUGHS CORPORATION

Inventor： BURROUGHS CORPORATION ,  SHETH, Jayesh, V.

IPC: G06F03/00

CPC classification number: G06F3/0601 ,  G06F13/124 ,  G06F2003/0698

Abstract: 13peripheral-controller (20t) (designated as a data-link-processor) manages data transfers between a main host computer (10) and a magnetic tape peripheral unit (MTU). The peripheral-controller uses a common front end (10c) providing an instruction sequencing unit (13) and a buffer memory (22) to store data-in-transit in six blocks of 256 words each. A peripheral-dependent circuit unit 80p1 or 80p2 of the peripheral-controller (20t) can provide automatic read or automatic write data transfers between the buffer memory (22) and the magnetic tape peripheral unit (MTU) without further attention from said instruction sequencing unit (13).

公开(公告)号：WO1985000448A1

公开(公告)日：1985-01-31

申请号：PCT/US1984001080

申请日：1984-07-11

Applicant: BURROUGHS CORPORATION

Inventor： BURROUGHS CORPORATION ,  PHELPS, Andrew, E. ,  LEVIN, Burton, L. ,  POTASH, Hanan

IPC: G06F01/00

CPC classification number: G06F12/1027

Abstract: An apparatus that translates virtual memory addresses into physical memory addresses. In particular, this apparatus comprises a plurality of rows of content addressable memory cells (32), a corresponding plurality of random access memory cells (35) and another corresponding plurality of control circuits (37). The content addressable memory cells (32) store the virtual memory addresses and the random access memory cells (35) store the physical memory addresses. The control circuits (37) are coupled to both the content addressable and the random access memory cells (32, 35) and are disposed for controlling the operation of the apparatus.

公开(公告)号：WO1984002421A1

公开(公告)日：1984-06-21

申请号：PCT/US1983001979

申请日：1983-12-16

Applicant: BURROUGHS CORPORATION

Inventor： BURROUGHS CORPORATION ,  BOLING, Norman ,  MAYER, Thomas ,  RANCOURT, James, D.

IPC: G11B07/24

CPC classification number: G11B7/2542 ,  G11B7/2585 ,  G11B2007/24316 ,  G11B2007/2571 ,  G11B2007/25715

Abstract: An optical data storage system is contemplated, one employing a data-modulated writing laser beam (LB) and a non-erasing reading laser beam (LB) of predetermined wavelength. Optical media for such systems are described, these characterized by multiple layers whose optical characteristics and thickness are chosen to accomodate a prescribed writing and reading energy and wavelength and so provide an "anti-reflection" condition for unrecorded portions of the medium and a relatively higher reflectivity for recorded portions. A preferred optical medium includes a highly reflective aluminum layer (e), a relatively transparent polymer spacer layer (d) overlying the reflective layer (c), and an optical absorber (recording) layer (e) overlying the spacer layer (d). Overcoating structure is specified in some detail: e.g., as a "soft pad" layer (f) (e.g., fluoropolymer) on the absorber (e), with a "Hard" layer (g) (e.g., radiation-cured acrylic) laid over the "soft pad" (f) as an outer protective overcoat. Also, the "spacer" may be rendered as such a "soft pad".

Abstract translation: 可以想到光学数据存储系统，一种采用预定波长的数据调制写入激光束（LB）和不擦除读取激光束（LB）。 描述了用于这种系统的光学介质，其特征在于多层，其光学特性和厚度被选择以适应规定的写入和读取能量和波长，并且因此为介质的未记录部分提供“防反射”条件，并且相对较高 记录部分的反射率。 优选的光学介质包括高反射性铝层（e），覆盖反射层（c）的相对透明的聚合物隔离层（d）和覆盖在间隔层（d）上的光吸收层（记录层）。 详细规定了涂层结构：例如，作为吸收体（e）上的“软垫”层（f）（例如含氟聚合物），铺设有“硬”层（g）（例如，辐射固化的丙烯酸树脂） 在“软垫”（f）上作为外部保护外套。 此外，“间隔物”可以被渲染为这样的“软垫”。

公开(公告)号：WO1984002395A1

公开(公告)日：1984-06-21

申请号：PCT/US1983001980

申请日：1983-12-16

Applicant: BURROUGHS CORPORATION

Inventor： BURROUGHS CORPORATION ,  MAYER, Thomas ,  BOLING, Norman, L. ,  RANCOURT, James, D.

IPC: G01D15/34

CPC classification number: G11B23/0014 ,  G11B7/2403 ,  G11B7/2542 ,  G11B7/2585 ,  G11B2007/24316 ,  G11B2007/2571 ,  G11B2007/25715 ,  Y10S428/913 ,  Y10S430/146 ,  Y10S430/162 ,  Y10T428/24802

Abstract: An optical data storage system is contemplated, one employing a data-modulated writing laser beam (1) and a non-erasing reading laser beam of predetermined wavelength. Improved optical media for such systems are described, these characterized by multiple layers whose optical characteristics and thickness are chosen to accomodate a prescribed writing and reading energy and wavelength and so provide an "anti-reflection" condition for unrecorded portions of the medium and a relatively higher reflectivity for recorded portions. A preferred optical medium includes a highly reflective aluminum layer (c), a relatively transparent polymer spacer layer (d) overlying the reflective layer, and an optical absorber (recording) layer (e) overlying the spacer layer. Overcoating structure is specified in some detail; e.g., as a "soft pad" layer (e.g., fluoropolymer (f)) on the absorber (e), with a "hard" layer (e.g., radiation-cured acrylic (g)) laid over the "soft pad" as an outer protective overcoat. Also, the "spacer" (d) may be rendered as such a "soft pad".

公开(公告)号：WO1984002247A1

公开(公告)日：1984-06-07

申请号：PCT/US1983001867

申请日：1983-11-29

Applicant: BURROUGHS CORPORATION

Inventor： BURROUGHS CORPORATION ,  ANDREADAKIS, Nicholas, C.

IPC: H05B37/00

CPC classification number: H01J11/00 ,  G08B13/187

Abstract: A gas-filled display panel (10) comprising a glass base plate (20) and a glass face plate (30) hermetically sealed together along a perimeter seal area to form an envelope which is filled with an ionizable gas, the base plate (20) having an array of longitudinal slots (40) in which anode wires (50) are seated and having an array of cathode electrodes (60) on the top surface (22) thereof. The base plate (20) has cross grooves (66, 68) transverse to the slots (40) and positioned one near each end of the base plate (20), and a glass rod (160) is secured in each cross groove (66, 68) with the ends of each rod (160) lying within the seal area between the base plate (20) and the face plate (30), the top surface of each insulating member (73) being generally coplanar with the top surface (22) of the base plate (20) in the seal area, to insure the formation of a hermetic seal between the base plate (20) and the face plate (30) at the cross grooves (66, 68).

公开(公告)号：WO1984002239A1

公开(公告)日：1984-06-07

申请号：PCT/US1983001803

申请日：1983-11-18

Applicant: BURROUGHS CORPORATION

Inventor： BURROUGHS CORPORATION ,  CLARK, Becky, Jane

IPC: H04J06/00

CPC classification number: H04L49/254 ,  G06F13/14 ,  G06F13/4022 ,  H04L49/103 ,  H04L49/40

Abstract: Arbiter (10) comprised of two input ports (11, 12) and one output port (13); each input port has N input data lines (D01...D0N and D11...Din), and the one output port has N output data lines (D1...DN); one circuit in the arbiter selects only one of the two input ports at a time; and another circuit in the arbiter passes characters from the selected input port to the output port. Each of the characters is represented by active logic signals on M-out-of-N data lines on the selected input port, with M being at least two and N being greater than M and greater than three.

公开(公告)号：WO1984001843A1

公开(公告)日：1984-05-10

申请号：PCT/US1983001707

申请日：1983-11-03

Applicant: BURROUGHS CORPORATION

Inventor： BURROUGHS CORPORATION ,  HORVATH, Carlos, Francisco

IPC: G06F09/26

CPC classification number: G06F9/3814 ,  G06F9/267

Abstract: A microcontroller for controlling a digital device without loss of clock cycles which controller is formed of a plurality of control stores (20a, 20b, 20c) each of which is provided with a register counter (21a, 21b, 21c) to address different locations within corresponding control store. Each control store is accessed each clock cycle and an instruction register (22) is provided to receive one of the fetched microinstructions from the selected control store. In this manner, a microinstruction is presented to the instruction register each clock cycle even though the previous microinstruction was a conditional branch, a jump to subroutine or a return to subroutine instruction. In order to accommodate jump to subroutine and corresponding return from subroutine instructions, arbitration logic (27) is provided to specify which control store is to provide the next microinstruction of the routine to which the jump is made and also which control store is to provide the next microinstruction after that routine is completed.