公开(公告)号：CA2675556C

公开(公告)日：2016-01-05

申请号：CA2675556

申请日：2008-01-16

Applicant: IBM

Inventor： MITRAN MARCEL ,  SHEIKH ALI

IPC: G06F11/34 ,  G06F9/455

Abstract: A handle for a trace is provided that is memory indifferent. The handle is created using contents of the trace rather than memory location of the trace. This enables the trace to be easily identified in subsequent runs of an application associated with the trace.

公开(公告)号：DE112013003079T5

公开(公告)日：2015-05-07

申请号：DE112013003079

申请日：2013-05-21

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY ,  MITRAN MARCEL

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

Abstract: Eine Anweisung TRANSACTION BEGIN und eine Anweisung TRANSACTION END werden bereitgestellt. Die Anweisung TRANSACTION BEGIN verursacht, dass abhängig von einem Feld der Anweisung entweder eine eingeschränkte oder eine nicht eingeschränkte Transaktion eingeleitet wird. Die Anweisung TRANSACTION END beendet die Transaktion, die durch die Anweisung TRANSACTION BEGIN gestartet wurde.

公开(公告)号：AU2012382777A1

公开(公告)日：2014-12-11

申请号：AU2012382777

申请日：2012-11-26

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY ,  MITRAN MARCEL

IPC: G06F9/06 ,  G06F9/44 ,  G06F9/45 ,  G06F9/54

Abstract: Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction.

公开(公告)号：AU2012382775A1

公开(公告)日：2014-12-11

申请号：AU2012382775

申请日：2012-11-22

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY ,  MITRAN MARCEL

IPC: G06F11/07

Abstract: When an abort of a transaction occurs in a computer system, a determination is made as to whether diagnostic information is to be stored in one or more transaction diagnostic blocks (TDBs). There are different types of transaction diagnostic blocks to accept diagnostic information depending on the type of abort and other considerations. As examples, there are a program-specified TDB in which information is stored if a valid TDB address is provided in a transaction begin instruction; a program interruption TDB, which is stored into when the program is aborted due to an interruption; and a program interception TDB, which is stored into when an abort results in an interception.

公开(公告)号：SG11201402090WA

公开(公告)日：2014-06-27

申请号：SG11201402090W

申请日：2012-11-13

Applicant: IBM

Inventor： CARLOUGH STEVEN ,  SCHWARZ ERIC MARK ,  SLEGEL TIMOTHY ,  GAINEY CHARLES JR ,  MITRAN MARCEL ,  COPELAND REID

IPC: G06F9/30

Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

公开(公告)号：SG11201402088PA

公开(公告)日：2014-06-27

申请号：SG11201402088P

申请日：2012-11-13

Applicant: IBM

Inventor： CARLOUGH STEVEN ,  SCHWARZ ERIC MARK ,  SLEGEL TIMOTHY ,  GAINEY CHARLES JR ,  MITRAN MARCEL ,  COPELAND REID

IPC: G06F9/30

Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

公开(公告)号：AU2012360180A1

公开(公告)日：2014-06-05

申请号：AU2012360180

申请日：2012-11-13

Applicant: IBM

Inventor： CARLOUGH STEVEN ,  SCHWARZ ERIC MARK ,  SLEGEL TIMOTHY ,  GAINEY JR CHARLES ,  MITRAN MARCEL ,  COPELAND REID

IPC: G06F9/30

Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

公开(公告)号：CA2866792A1

公开(公告)日：2013-09-19

申请号：CA2866792

申请日：2013-03-01

Applicant: IBM

Inventor： FARRELL MARK S ,  GAINEY CHARLES W JR ,  MITRAN MARCEL ,  SHUM CHUNG-LUNG KEVIN ,  SLEGEL TIMOTHY ,  SMITH BRIAN LEONARD ,  STOODLEY KEVIN A

IPC: G06F11/34

Abstract: Embodiments of the invention relate to enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. It is determined, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction. The enabling includes updating the bit in the PSW to indicate that run-time instrumentation data should be captured by the processor.

公开(公告)号：MX2012014532A

公开(公告)日：2013-04-03

申请号：MX2012014532

申请日：2010-11-08

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  MITRAN MARCEL

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/305 ,  G06F9/312

Abstract: Se ejecuta una instrucción aritmética/lógica que tiene operandos de memoria enclavados, cuando se ejecuta obtiene un segundo operando de una ubicación de memoria y guarda una copia temporal del segundo operando, la ejecución realiza una operación aritmética o lógica con base en el segundo operando y un tercer operando y almacenar el resultado en la ubicación de memoria del segundo operando, y subsecuentemente almacena la copia temporal en un primer registro.

公开(公告)号：ZA201108701B

公开(公告)日：2012-08-29

申请号：ZA201108701

申请日：2011-11-25

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  MITRAN MARCEL

IPC: G06F20060101

Abstract: An arithmetic/logical instruction is executed having interlocked memory operands. when executed obtains a second operand from a location in memory, and saves a temporary copy of the second operand, the execution performs an arithmetic or logical operation based on the second operand and a third operand and stores the result in the memory location of the second operand, and subsequently stores the temporary copy in a first register.