公开(公告)号：US20170221828A1

公开(公告)日：2017-08-03

申请号：US15445805

申请日：2017-02-28

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L21/02

CPC classification number: H01L23/5385 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/4821 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

公开(公告)号：US09673131B2

公开(公告)日：2017-06-06

申请号：US13859659

申请日：2013-04-09

Applicant: Intel Corporation

Inventor： Chuan Hu ,  Qing Ma ,  Chia-Pin Chiu

IPC: H01L23/52 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49894 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for integrated circuit package assemblies including a glass solder mask layer and/or bridge. In one embodiment, an apparatus includes one or more build-up layers having electrical routing features and a solder mask layer composed of a glass material, the solder mask layer being coupled with the one or more build-up layers and having openings disposed in the solder mask layer to allow coupling of package-level interconnect structures with the electrical routing features through the one or more openings. Other embodiments may be described and/or claimed.

公开(公告)号：US09349703B2

公开(公告)日：2016-05-24

申请号：US14036719

申请日：2013-09-25

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kinya Ichikawa ,  Robert L. Sankman

IPC: H01L21/44 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H05K1/11 ,  H05K3/34 ,  H05K3/46

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/23 ,  H01L24/24 ,  H01L24/25 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/215 ,  H01L2224/24225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15747 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/4664 ,  H05K3/4694 ,  H05K2203/013 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.

Abstract translation: 这里通常讨论的是包括密集互连桥和其制造技术的系统和装置。 根据一个示例，一种技术可以包括创建多芯基板，在多芯基板上印刷互连桥，通过将第一和第二裸片耦合通过互连桥将第一裸片电耦合到第二裸片。

公开(公告)号：US20160079196A1

公开(公告)日：2016-03-17

申请号：US14922425

申请日：2015-10-26

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/50 ,  H01L25/18

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US09275971B2

公开(公告)日：2016-03-01

申请号：US14495396

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

IPC: H01L21/28 ,  H01L21/76 ,  H01L23/00 ,  H01L23/538 ,  H01L21/02 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L23/5385 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/4821 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及可嵌入封装组件中的桥互连组件的技术和配置。 在一个实施例中，包装组件包括被配置为在第一管芯和第二管芯之间布置电信号的封装衬底和嵌入在封装衬底中并被配置为在第一管芯和第二管芯之间布置电信号的桥， 包括桥接基板，通过桥接基板形成的一个或多个通孔通孔（THV）和布置在桥接基板的表面上的一个或多个走线，以在第一管芯和第二管芯之间布置电信号。 包括迹线和桥互连组件的接地平面的布线特征可以由气隙分开。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09263329B2

公开(公告)日：2016-02-16

申请号：US14219749

申请日：2014-03-19

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kinya Ichikawa ,  Yoshihiro Tomita ,  Robert L. Sankman ,  Eric Li

IPC: H01L21/00 ,  H01L21/4763 ,  H01L21/768 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/11 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81801 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/01029 ,  H01L2924/06 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/381

Abstract: A method of fabricating an electronic package. The method includes filling a mold with an electric conductor to form a number of electrical interconnects within the mold. The mold includes openings that are filled with several electric conductors to form a number of electrical interconnects. The method of fabricating an electronic package further includes attaching the mold to a substrate such that the electrical interconnects engage electrical contacts on the substrate. The method of fabricating an electronic package may further include forming conductive pads on the electrical insulator that engage the electrical interconnects and attaching a die to the substrate such that the die is electrically connected to at least some of the electrical interconnects.

Abstract translation: 一种制造电子封装的方法。 该方法包括用电导体填充模具以在模具内形成多个电互连。 模具包括填充有多个电导体以形成多个电互连的开口。 制造电子封装的方法还包括将模具附接到基板，使得电互连件接合基板上的电触点。 制造电子封装的方法还可以包括在电绝缘体上形成接合电互连并将管芯连接到衬底上的导电焊盘，使得管芯电连接到至少一些电互连。

公开(公告)号：US20160043049A1

公开(公告)日：2016-02-11

申请号：US14879418

申请日：2015-10-09

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Xiaorong Xiong ,  Linda Zhang ,  Robert Nickerson ,  Charles Gealer

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L24/13 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11013 ,  H01L2224/1132 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/1815 ,  H01L2924/00

Abstract: Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. According to an example, a technique can include forming a circuit substrate including forming a circuit on a substrate, the circuit exposed along an upper surface of the substrate, wherein the substrate is for coupling the circuit with a die along a lower surface of the circuit substrate. A molding can be formed onto an upper surface of the circuit substrate, over the circuit of the circuit substrate. An opening can be defined in the molding so that the opening can extend to a top surface of the molding to at least a portion of the circuit. Solder can be formed into the opening, including conforming the solder to the opening and the circuit substrate.

公开(公告)号：US09159690B2

公开(公告)日：2015-10-13

申请号：US14036755

申请日：2013-09-25

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Xiaorong Xiong ,  Linda Zhang ,  Robert Nickerson ,  Charles Gealer

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11013 ,  H01L2224/1132 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/1815 ,  H01L2924/00

Abstract: Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. A package can include a chip package situated below a lower surface of a first substrate, the package including a die situated on a top surface of a second substrate, a molding disposed over the upper surface of the second substrate, the molding extending over the second die and including an opening extending from an upper surface of the molding towards an upper surface of the second substrate, wherein the opening is configured to admit at least a portion of the solder ball, and a solder column electrically and mechanically coupled to the second substrate, situated in the opening, conforming to the cylinder, and including at least two layers of solder with flux therebetween.

Abstract translation: 本文通常讨论的是包括扩展TSBA球的系统和装置及其制造技术。 封装可以包括位于第一基板的下表面下方的芯片封装，所述封装包括位于第二基板的顶表面上的模具，设置在所述第二基板的上表面上的模具，所述模制件在所述第二基板的上表面上延伸 并且包括从模制件的上表面朝向第二基板的上表面延伸的开口，其中开口被配置为允许焊球的至少一部分，并且焊料柱电和机械地耦合到第二基板 ，位于开口中，符合气缸，并且包括至少两层焊料，焊剂之间具有焊剂。