公开(公告)号：US11417630B2

公开(公告)日：2022-08-16

申请号：US16349543

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Digvijay A. Raorane ,  Ravindranath Vithal Mahajan ,  Mitul Bharat Modi

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/822 ,  H01L23/31 ,  H01L23/42 ,  H01L23/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L23/498 ,  H01L23/367

Abstract: Semiconductor packages including passive support wafers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes a passive support wafer mounted on several active dies. The active dies may be attached to an active die wafer, and the passive support wafer may include a monolithic form to stabilize the active dies and active die wafer during processing and use. Furthermore, the passive support wafer may include a monolith of non-polymeric material to transfer and uniformly distribute heat generated by the active dies.

公开(公告)号：US20210305121A1

公开(公告)日：2021-09-30

申请号：US16831068

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Je-Young Chang ,  Ram Viswanath ,  Elah Bozorg-Grayeli ,  Ahmad Al Mohammad

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L23/373 ,  H01L23/18 ,  H01L21/48

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

公开(公告)号：US20210272905A1

公开(公告)日：2021-09-02

申请号：US16804835

申请日：2020-02-28

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Debendra Mallik ,  Nitin A. Deshpande ,  Amruthavalli Pallavi Alur

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/522 ,  H01L23/498 ,  H01L23/00

Abstract: Embodiments may relate to a microelectronic package that includes a substrate with a cavity therein. A component may be positioned within the substrate, and exposed by the cavity. A solder bump may be positioned within the cavity and coupled with the component, and a bridge die may be coupled with the solder bump. Other embodiments may be described or claimed.

公开(公告)号：US20210242104A1

公开(公告)日：2021-08-05

申请号：US17234671

申请日：2021-04-19

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Digvijay Raorane

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/495

Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US11011448B2

公开(公告)日：2021-05-18

申请号：US16529617

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Digvijay Raorane

IPC: H01L23/34 ,  H01L21/00 ,  H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/495

Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US10658765B2

公开(公告)日：2020-05-19

申请号：US16021474

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Sanka Ganesan ,  William J. Lambert ,  Debendra Mallik ,  Zhichao Zhang

IPC: H01Q1/38 ,  H01Q25/00 ,  H01Q9/04

Abstract: A method of forming a planar antenna on a first substrate. An antenna feedline is formed on a peelable copper film of a carrier. A dielectric with no internal conductive layer is formed on the feedline. A planar antenna is formed on one of two parallel sides of the dielectric and a feed port is formed adjacent the other parallel side. The feedline connects the antenna with the feed port. One plane of the planar antenna is configured for perpendicular attachment to a second substrate. The feedline is connected to the planar antenna by a via through the dielectric. The peelable copper is removed and the structure is etched to produce the planar antenna on the substrate. Two planar antennas on substrates can be perpendicularly attached to another substrate to form side-firing antennas.

公开(公告)号：US10403512B2

公开(公告)日：2019-09-03

申请号：US15899222

申请日：2018-02-19

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/16

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US09899238B2

公开(公告)日：2018-02-20

申请号：US14576166

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L21/563 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81211 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US09711441B2

公开(公告)日：2017-07-18

申请号：US14963215

申请日：2015-12-08

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Mihir Roy

IPC: H01L23/52 ,  H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2224/16225 ,  H05K1/113 ,  H05K1/115

Abstract: Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.

公开(公告)号：US09679843B2

公开(公告)日：2017-06-13

申请号：US15049500

申请日：2016-02-22

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L23/48 ,  H01L23/522 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.