公开(公告)号：US20210014450A1

公开(公告)日：2021-01-14

申请号：US16939742

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Joydeep Ray ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Michael Apodaca ,  Murali Ramadoss ,  Abhishek Venkatesh

IPC: H04N5/911

Abstract: Systems, apparatuses and methods may provide for technology that determines a frame rate of video content, sets a blend amount parameter based on the frame rate, and temporally anti-aliases the video content based on the blend amount parameter. Additionally, the technology may detect a coarse pixel (CP) shading condition with respect to one or more frames in the video content and select, in response to the CP shading condition, a per frame jitter pattern that jitters across pixels, wherein the video content is temporally anti-aliased based on the per frame jitter pattern. The CP shading condition may also cause the technology to apply a gradient to a plurality of color planes on a per color plane basis and discard pixel level samples associated with a CP if all mip data corresponding to the CP is transparent or shadowed out.

公开(公告)号：US10803656B2

公开(公告)日：2020-10-13

申请号：US16539007

申请日：2019-08-13

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T15/50 ,  G06T15/00 ,  G06T15/80 ,  G06T17/20

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

公开(公告)号：US10748234B2

公开(公告)日：2020-08-18

申请号：US16024750

申请日：2018-06-30

Applicant: INTEL CORPORATION

Inventor： Michael Apodaca

IPC: G06T1/20 ,  G06F1/32 ,  G06F15/76 ,  G06F1/329 ,  G06F1/3212 ,  G06F1/3234

Abstract: Various embodiments are presented herein that may reduce the workload of a system tasked with delivering frames of video data to a display generated by applications executing within the system. Applications executing within the system may generate new frames of video content at a specified frame rate known as frames per second (FPS). The CPU and/or GPU may be responsible for actually generating the frames at the specified FPS. These frames are then delivered to a display communicatively coupled with the system for rendering. Reducing the frame rate (FPS) may reduce the work being performed by the system because fewer frames may be generated within a given time period. This may be especially advantageous when the system is operating on battery power because it can extend the life of the battery.

公开(公告)号：US20200257532A1

公开(公告)日：2020-08-13

申请号：US16794973

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  Abhishek R. Appu

IPC: G06F9/30 ,  G06T1/20 ,  G09G5/36 ,  G06T15/00 ,  G06F9/50

Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.

公开(公告)号：US20200219223A1

公开(公告)日：2020-07-09

申请号：US16243624

申请日：2019-01-09

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Brandon Fliflet ,  James Valerio ,  Michael Apodaca ,  Ben Ashbaugh ,  Hema Nalluri ,  Ankur Shah ,  Murali Ramadoss ,  David Puffer ,  Altug Koker ,  Aditya Navale ,  Abhishek R. Appu ,  Joydeep Ray ,  Travis Schluessler

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/48 ,  G06F9/52 ,  G06F9/50

Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.

公开(公告)号：US10699475B1

公开(公告)日：2020-06-30

申请号：US16235517

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Joshua Barczak ,  Kai Xiao ,  Michael Apodaca ,  Thomas Raoux ,  Carson Brownlee ,  Gabor Liktor

IPC: G06T15/40 ,  G06T15/04 ,  G06T15/00 ,  G06T15/06

Abstract: Multi-pass apparatus and method for ray tracing shading. For example, one embodiment of an apparatus comprises: graphics processing circuitry to execute a sequence of visibility testing operations related to texels within a texture domain to generate visibility results; a register or memory to store a texel mask; texel mask update circuitry/logic to update the texel mask based on the visibility results, the texel mask comprising a plurality of bits to indicate visibility of the texels within the texture domain, the texel mask update circuitry/logic to set a first bit to indicate whether any bits in the texel mask indicate a visible texel; a shader dispatcher to initiate conditional dispatch operations only if the first bit is set to indicate that at least one bit in the texel mask indicates a visible texel, wherein to perform the conditional dispatch operations, the shader dispatcher is to dispatch texel shaders for only those texels that the texel mask indicates may be visible; and a plurality of execution units (EUs) to execute the shaders dispatched by the shader dispatcher.

公开(公告)号：US10572258B2

公开(公告)日：2020-02-25

申请号：US15477012

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  Abhishek R. Appu

IPC: G06F9/30 ,  G06F9/50 ,  G06T15/00 ,  G09G5/36 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.

公开(公告)号：US20200043224A1

公开(公告)日：2020-02-06

申请号：US16539007

申请日：2019-08-13

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T15/50 ,  G06T15/00 ,  G06T15/80 ,  G06T17/20

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

公开(公告)号：US20190259127A1

公开(公告)日：2019-08-22

申请号：US16237987

申请日：2019-01-02

Applicant: Intel Corporation

Inventor： Abhishek Venkatesh ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T1/20 ,  G06T15/00 ,  G06F9/30 ,  G06F9/38

Abstract: An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.

公开(公告)号：US10379611B2

公开(公告)日：2019-08-13

申请号：US15268494

申请日：2016-09-16

Applicant: Intel Corporation

Inventor： Tomas G. Akenine-Moller ,  Robert M. Toth ,  Ingo Wald ,  Aditya S. Yanamandra ,  Brent E. Insko ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06F3/01 ,  G06T1/20 ,  G06T3/00 ,  G06T19/00 ,  G06T15/00

Abstract: A virtual reality apparatus and method are described. For example, one embodiment of an apparatus comprises: a compute cluster comprising global illumination circuitry and/or logic to perform global illumination operations on graphics data in response to execution of a virtual reality application and to responsively generate a stream of samples; a filtering/compression module to perform filtering and/or compression operations on the stream of samples to generate filtered/compressed samples; a network interface to communicatively couple the compute cluster to a network, the filtered/compressed samples to be streamed over the network; a render node to receive the filtered/compressed samples streamed over the network, the render node comprising: decompression circuitry/logic to decompress the filtered/compressed samples to generate decompressed samples; a sample buffer to store the decompressed samples; and sample insertion circuitry/logic to asynchronously insert samples into a light field rendered by a light field rendering circuit/logic.