公开(公告)号：JP2001076439A

公开(公告)日：2001-03-23

申请号：JP25176899

申请日：1999-09-06

Applicant: SONY CORP

Inventor： KAWASHIMA TETSUJI

IPC: G11B20/14 ,  H03L7/08 ,  H03L7/085 ,  H03L7/087

Abstract: PROBLEM TO BE SOLVED: To reproduce and output an accurate form clock from a binary signal outputted from an optical disk device corresponding to speed-up of the optical disk device. SOLUTION: A phase comparator (PD1) 1 outputs a phase error signal limited at a coming out timing of a rising edge of a binary signal. A phase comparator (PD2) 2 outputs a phase error signal limited at coming out timing of a falling edge of the binary signal. Respective outputs of the phase comparators (PD1) 1, (PD2) 2 and a frequency meter (FD) 3 are summed at the pre-stage of a low-pass filter(LPF) 4. A voltage controlled oscillator(VCO) 5 controls an oscillation frequency according to the output signal of the low-pass filter(LPF) 4, and reproduces and outputs a clock signal having an N-fold frequency of the clock signal (PLCK). A frequency divider (1/N) 6 divides the output signal of the above-mentioned voltage controlled oscillator and outputs the clock signal (PLCK).

公开(公告)号：JP2000224031A

公开(公告)日：2000-08-11

申请号：JP2491699

申请日：1999-02-02

Applicant: SONY CORP

Inventor： KAWASHIMA TETSUJI

IPC: G11B20/14 ,  H03L7/087 ,  H03L7/093

Abstract: PROBLEM TO BE SOLVED: To make the output terminals of a phase comparator and a frequency comparator usable in common. SOLUTION: This PLL circuit is provided with a VCO 36, which is controlled by a frequency control signal OUT-POL and generates a clock PLCK, a frequency comparing section 31 which compares the frequency of a reproduced signal with the oscillation frequency of the clock PLCK and outputs the difference between the two frequencies, and a phase comparing section 30 which compares the phase of the reproduced signal with that of the clock PLCK and detects and outputs the difference between the two phases. The PLL circuit is also provided with a frequency control signal generating section 32, which generates the frequency control signal OUT-POL based on the detecting outputs of the comparing section 30 and 31, an output control signal generating section 33, which outputs an output control signal OUT-ENA which controls the output of the signal OUT-POL, based on the detecting outputs of the comparing sections 30 and 31, and an output buffer 34 which is caused to output the signal OUT-POL to the VCO 36 based on the signal OUT-ENA.

公开(公告)号：JP2000067511A

公开(公告)日：2000-03-03

申请号：JP23879798

申请日：1998-08-25

Applicant: SONY CORP

Inventor： KAWASHIMA TETSUJI ,  SHISHIDO YUKIO

IPC: G11B20/10 ,  G11B19/02 ,  G11B19/28

Abstract: PROBLEM TO BE SOLVED: To efficiently utilize the max. data transfer rate. SOLUTION: This reproducing device has a disk rotating means which is capable of rotating a loaded disk at a specified angular speed, a capacity detecting means which detects the logic block address of the data recorded in the outermost periphery of the data area recorded with the data as the data capacity recorded on the disk from a control information area of the disk and a control means which executes the control of the disk rotating means in accordance with the data capacity detected by the capacity detecting means. The device sets the disk rotating speed according to the data capacity (S007, S009, S010, S014, S016), S017).

公开(公告)号：JPH11110904A

公开(公告)日：1999-04-23

申请号：JP27237797

申请日：1997-10-06

Applicant: SONY CORP

Inventor： SATO MASASHI ,  KOBAYASHI SHUICHI ,  KAWASHIMA TETSUJI

IPC: G11B19/28

Abstract: PROBLEM TO BE SOLVED: To realize a constant linear velocity(CLV) system optical disk device in which the power consumption is low, vibration is reduced and a high speed access is made possible. SOLUTION: In the CLV system optical disk device, the target linear velocity value, which is normally constant, is controlled to a prescribed value in accordance with the situation. In the case of a random access, at the time just after seeking, the revolving speed of a disk is measured, an actual line velocity corresponding to the revolving speed is set as a temporary target value. Then, the value is gradually increased or decreased until the value reaches to the normal reference value corresponding to a desired address depending on whether a seek direction is the inner peripheral side or the outer peripheral side of the disk.

公开(公告)号：JPH1097768A

公开(公告)日：1998-04-14

申请号：JP26771596

申请日：1996-09-19

Applicant: SONY CORP

Inventor： KAWASHIMA TETSUJI

IPC: G11B20/14 ,  G11B7/00 ,  G11B7/005 ,  H03L7/085

Abstract: PROBLEM TO BE SOLVED: To prevent the occurrence of phase deviation in phase error information outputted from a phase comparator even when a clock frequency becomes high. SOLUTION: Phase error information PDO outputted from a phase comparator is made a ternary signal of a first value (H), a second value (L), and a third value (Hi-Z), and when signals of the first value and the third value are outputted, the signals of the first value and the third value are continuously outputted. Thereby, even when a clock frequency is high, phase deviation caused by waveform distortion of outputted phase error information PDO is prevented.

公开(公告)号：JPH1069733A

公开(公告)日：1998-03-10

申请号：JP24543396

申请日：1996-08-29

Applicant: SONY CORP

Inventor： SATO MASASHI ,  KAWASHIMA TETSUJI

IPC: G11B20/14

Abstract: PROBLEM TO BE SOLVED: To generate a synchronous clock in a short time by making a PLL operation after feeding a prescribed voltage value in accordance with a measured value to the voltage controlled oscillator provided in a PLL circuit and generating the clock synchronized with a reading signal. SOLUTION: Digital voltage information in accordance with the absolute frequency value measured with a frequency measuring instrument 5 from a micro computer 7 is read from a RAM 8 and outputted to a D/A converter 9. An analog voltage VE in accordance with the absolute frequency measured value is outputted to an adder 15 from the converter 9. Also, the voltage of a LPF 14 is discharged with the micro computer 7. Accordingly, the oscillating frequency of a VCO 16 is controlled with the voltage VE outputted from the converter 9, each of the voltages V1 -Vn is set as the voltage value for generating frequencies f1 -fn in the VCO 16, whereby the oscillating frequency of the VCO 16 becomes the frequency near the frequency of an EFM signal read from a disk 1 after seeking.

公开(公告)号：JPH0836776A

公开(公告)日：1996-02-06

申请号：JP17220694

申请日：1994-07-25

Applicant: SONY CORP

Inventor： KAWASHIMA TETSUJI

IPC: G11B7/135

Abstract: PURPOSE:To increase the objective lens focal length with invariable lens numerical aperture and to reduce in size optical system components by increasing the beam diameter on the objective lens by a light diverging means. CONSTITUTION:A laser light emitted from the laser diode 10 of a light source is cast at an optical disk 13 via a rising mirror 11 and an objective lens 12 as convergent light, and received by a photosensor 15 via a half mirror 14. In this optical system, a convex mirror is used as the mirror 11 to be the light diverging means. Thus, a beam diameter on the lens 12 can be increased, a lens numerical aperture is made invariable, and the focal length of the lens 12 can be increased. Accordingly, optical system components can be reduced in size in the state that an operating distance WD necessary between the lens 12 and the disk 13 is obtained.

公开(公告)号：JPH05101302A

公开(公告)日：1993-04-23

申请号：JP28041891

申请日：1991-10-01

Applicant: SONY CORP

Inventor： WACHI SHIGEAKI ,  KAWASHIMA TETSUJI

IPC: G11B5/02 ,  G11B11/10 ,  G11B11/105

Abstract: PURPOSE:To improve the switching characteristic of the driving circuit of a magnetic modulation coil and to obtain effective magnetic force. CONSTITUTION:When a field effect transistor (FET) 8 is turned on and the FET 9 is turned off from a state the FET 8 is turned off and the FET 9 is turned on, current flowing through a coil 14 through a series circuit of a resistor 12 and the coil 10 flows through the drain of the FET 8. Further, the current flowing through the drain of the FET 9 through the series circuit of the resistor 13 and the coil 11 is interrupted in a moment. At this time, though the current, as well flowing through the coil 11 is interrupted, when the current flowing through the coil 11 is changed, counter electromotive force is generated in the coil 11 so as to cancel the change. Thus, since the current flows through the drain of the FET 8 in a moment through the coil 14 by the counter electromotive force, the magnetic force is generated in a moment in the coil 14.

公开(公告)号：JPH04356731A

公开(公告)日：1992-12-10

申请号：JP2506391

申请日：1991-01-28

Applicant: SONY CORP

Inventor： KAWASHIMA TETSUJI

IPC: G11B7/00 ,  G11B7/005 ,  G11B20/14

Abstract: PURPOSE:To improve a clamp circuit used in the clock regeneration circuit of a sample servo system optical disk such as to extract a clock by a PLL circuit. CONSTITUTION:A reproduced RF signal is detected by a rectification circuit EDC through a buffer amplifier B a mask control switch MS, and the buffer amplifier B2, and detected voltage ED corresponding to the peak level (reflected light at mirror surface) of the reproduced RF signal is supplied to a comparator C1. The comparator C1 detects the reproduced RF signal by making the detected voltage ED a reference level, but a system is constituted so that the peak value of the above-mentioned detected voltage ED is prevented from varying large by making the above-mentioned mask control switch MS select earth voltage EO, for instance, during a period that strong reflected light is outputted in the data recording area of the optical disk. Since clamping operation is executed surely, and the clock can be extracted even when the PLL circuit is not locked, the system can be surely started. Besides, at the time of recording data as well, the PLL circuit can be surely held in a locked state.

公开(公告)号：JPH03201268A

公开(公告)日：1991-09-03

申请号：JP33652989

申请日：1989-12-27

Applicant: SONY CORP

Inventor： CHIAKI SUSUMU ,  KAWASHIMA TETSUJI

IPC: G11B20/14

Abstract: PURPOSE:To obtain an external clock signal suitable for reproducing data by correcting a phase of the external clock signal based on a regenerative signal of a reference clock signal at the time of reproducing the data. CONSTITUTION:One segment Sg is composed of a servo area 1 and a data area 2, and in the servo area 1, one pair of wobble pits for obtaining the so- called tracking error signal and clock pits for the purpose of synchronizing a clock are provided in advance, while in the data area 2, a data is recorded or reproduced by utilizing the magneto-optical effect. Then, in order to dissolve a problem caused by a phase shift, a reference clock signal and a constant level signal are recorded, for instance, in the data area 2 of the 2nd segment. A regenerative signal of the reference clock signal recoded to a recording medium in this way is sampled by using the external clock signal having a different phase from each other, and the external clock signal having such a phase that a difference from this sample value is a max. is selected. By this way, the external clock signal suitable for reproducing data can be obtained.